JP2012504326A - 基板全域にわたって高められた均一性を有する埋め込みSi/Ge材質を伴うトランジスタ - Google Patents
基板全域にわたって高められた均一性を有する埋め込みSi/Ge材質を伴うトランジスタ Download PDFInfo
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Abstract
洗練された半導体デバイスにおいては、異なる結晶方位に対して異方性エッチング挙動を有し得るウエット化学的エッチングプロセスに基いてキャビティを形成することによって、チャネル領域の近くに歪誘起半導体合金を位置させることができる。1つの実施形態では、異方性エッチング挙動に加えて二酸化シリコンに関する高いエッチング選択性を呈するTMAHを用いることができ、それにより、チャネル領域からのオフセットを更に減少させる可能性を追加的に提供する一方で、全体的なプロセスばらつきの大きな原因となることのない極めて薄いエッチング停止層が可能になる。
【選択図】図2c
Description
Claims (25)
- シリコン含有結晶性半導体領域の上方に形成されるトランジスタのゲート電極構造の露出させられた表面区域上に誘電体エッチング停止材質を形成することと、
前記結晶性半導体領域の少なくとも2つの異なる結晶方位において異なる除去速度を有するウエット化学的エッチングプロセスを実行することによって前記ゲート電極構造に隣接する前記結晶性半導体領域内にキャビティを形成することと、
選択的エピタキシャル成長プロセスを実行することによって少なくとも前記キャビティ内に歪誘起半導体合金を形成することと、
前記歪誘起半導体合金の少なくとも一部分内にドレイン及びソース領域を形成することとを備えた方法。 - 前記ウエット化学的エッチングプロセスはテトラメチルアンモニウムヒドロキシド(TMAH)に基いて実行される、請求項1の方法。
- 前記誘電体エッチング停止材質を形成することは前記ゲート電極構造の少なくとも側壁表面上に二酸化シリコン層を形成することを備えている、請求項1の方法。
- 前記二酸化シリコン層の厚みは概ね5ナノメートル以下である、請求項3の方法。
- n型ドーパント種を前記結晶性半導体領域内の特定の深さに位置させることと、前記n型ドーパント種を用いて前記ウエット化学的エッチングプロセスを制御することとを更に備えた、請求項1の方法。
- 前記n型ドーパント種はイオン注入プロセスを実行することによって前記特定の深さに位置させられる、請求項5の方法。
- 前記イオン注入プロセスは前記ゲート電極構造を形成することに先立ち実行される、請求項6の方法。
- 前記イオン注入プロセスは前記ゲート電極構造を形成することの後に実行される、請求項6の方法。
- 前記結晶性半導体領域はエピタキシャル成長プロセスによって形成され、
前記n型ドーパント種は前記エピタキシャル成長プロセスの間に前記特定の深さに位置させられる、請求項5の方法。 - 前記半導体合金は前記トランジスタのチャネル領域内に圧縮歪を誘起するように形成される、請求項5の方法。
- 前記半導体合金はシリコン及びゲルマニウムから構成されている、請求項10の方法。
- 前記半導体合金は錫を備えている、請求項10の方法。
- 結晶性半導体領域の一部分の上方に形成されるトランジスタのゲート電極構造に隣接する前記結晶性半導体領域内に、テトラメチルアンモニウムヒドロキシド(TMAH)に基くウエット化学的エッチングプロセスを実行することによってキャビティを形成することと、
前記キャビティ内に歪誘起半導体合金を形成することと、
前記ゲート電極構造に隣接する前記半導体領域内にドレイン及びソース領域を形成することとを備えた方法。 - 前記キャビティを形成することは、n型ドーパント種を前記半導体領域内の特定の深さに位置させることと、前記n型ドーパント種を用いて前記ウエット化学的エッチングプロセスを制御することとを更に備えている、請求項13の方法。
- 前記キャビティを形成することに先立ちゲート電極材質の少なくとも側壁上にエッチング停止材質を形成することを更に備えた、請求項13の方法。
- 前記エッチング停止材質は概ね5ナノメートル以下の厚みを有している、請求項15の方法。
- 前記ドレイン及びソース領域を形成することは前記キャビティ内に半導体合金を形成することを備えており、
前記半導体合金は前記トランジスタのチャネル領域内に圧縮歪を誘起する、請求項13の方法。 - 前記キャビティを形成し、そして前記キャビティ内に前記半導体合金を形成する間に第2のトランジスタの上方にマスク層を設けることを更に備えた、請求項17の方法。
- 前記半導体合金はゲルマニウム及び錫の少なくとも一方を備えている、請求項17の方法。
- 基板の上方に形成されるトランジスタを備えた半導体デバイスであって、
前記トランジスタは、
結晶性半導体領域の上方に形成され、ゲート電極材質を備えているゲート電極構造と、
概ね30°以上の側壁角度で先細になる様態で深さ方向に沿って延びるように前記結晶性半導体領域内に形成される歪誘起半導体合金と、
前記結晶性半導体領域内に且つ少なくとも部分的に前記半導体合金内に形成されるドレイン及びソース領域とを備えている半導体デバイス。 - 前記半導体合金の底を中心として増加させられたn型ドーパント濃度を更に備えた、請求項20の半導体デバイス。
- 前記ゲート電極材質からの前記半導体合金の最小横方向オフセットは概ね5ナノメートル以下である、請求項20の半導体デバイス。
- 前記ゲート電極材質からの前記半導体合金の最小横方向オフセットは概ね2ナノメートル以下である、請求項22の半導体デバイス。
- 前記半導体合金は前記トランジスタのチャネル領域内に圧縮歪を誘起する、請求項20の半導体デバイス。
- 前記ゲート電極材質のゲート長は概ね50ナノメートル以下である、請求項24の半導体デバイス。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008049723A DE102008049723B4 (de) | 2008-09-30 | 2008-09-30 | Transistor mit eingebettetem Si/Ge-Material mit einer besseren substratüberspannenden Gleichmäßigkeit |
DE102008049723.1 | 2008-09-30 | ||
US12/562,437 US8183100B2 (en) | 2008-09-30 | 2009-09-18 | Transistor with embedded SI/GE material having enhanced across-substrate uniformity |
US12/562,437 | 2009-09-18 | ||
PCT/EP2009/007001 WO2010037522A1 (en) | 2008-09-30 | 2009-09-29 | A transistor with embedded si/ge material having enhanced across-substrate uniformity |
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JP2012504326A true JP2012504326A (ja) | 2012-02-16 |
JP2012504326A5 JP2012504326A5 (ja) | 2012-11-15 |
JP5798923B2 JP5798923B2 (ja) | 2015-10-21 |
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JP2011528255A Active JP5798923B2 (ja) | 2008-09-30 | 2009-09-29 | 基板全域にわたって高められた均一性を有する埋め込みSi/Ge材質を伴うトランジスタ |
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US (2) | US8183100B2 (ja) |
JP (1) | JP5798923B2 (ja) |
KR (1) | KR20110081942A (ja) |
CN (1) | CN102160159A (ja) |
DE (1) | DE102008049723B4 (ja) |
WO (1) | WO2010037522A1 (ja) |
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DE102008049723B4 (de) * | 2008-09-30 | 2012-01-26 | Advanced Micro Devices, Inc. | Transistor mit eingebettetem Si/Ge-Material mit einer besseren substratüberspannenden Gleichmäßigkeit |
US8492234B2 (en) * | 2010-06-29 | 2013-07-23 | International Business Machines Corporation | Field effect transistor device |
US9006052B2 (en) | 2010-10-11 | 2015-04-14 | International Business Machines Corporation | Self aligned device with enhanced stress and methods of manufacture |
DE102010064282B4 (de) * | 2010-12-28 | 2012-09-06 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Transistor mit eingebetteten sigma-förmigen sequenziell hergestellten Halbleiterlegierungen |
US9018065B2 (en) * | 2012-05-08 | 2015-04-28 | Globalfoundries Inc. | Horizontal epitaxy furnace for channel SiGe formation |
US9054217B2 (en) | 2013-09-17 | 2015-06-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device having an embedded source/drain |
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US8334569B2 (en) | 2012-12-18 |
KR20110081942A (ko) | 2011-07-15 |
CN102160159A (zh) | 2011-08-17 |
US20100078691A1 (en) | 2010-04-01 |
JP5798923B2 (ja) | 2015-10-21 |
US8183100B2 (en) | 2012-05-22 |
DE102008049723A1 (de) | 2010-04-08 |
WO2010037522A1 (en) | 2010-04-08 |
US20120211810A1 (en) | 2012-08-23 |
DE102008049723B4 (de) | 2012-01-26 |
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