JP2009514249A - 薄層soiトランジスタに埋め込まれた歪み層ならびにその形成法 - Google Patents
薄層soiトランジスタに埋め込まれた歪み層ならびにその形成法 Download PDFInfo
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Abstract
Description
加えて、ゲート絶縁層に対して垂直のPN接合の位置はさらに、漏れ電流制御の点でクリティカルなデザイン基準を表す。よって、チャネル長を縮小するには、ゲート絶縁層およびチャネル領域によって形成されるインターフェースに対してドレインおよびソース領域の深さも低くしなければならず、これにより洗練されたインプラント技術が要求される。別のアプローチによれば、隆起したドレインおよびソース領域と呼ばれるエピタキシャル成長した領域が、ゲート電極に対して特定のオフセットを備えて形成され、この隆起したドレインおよびソース領域の導電性が増加される一方で、ゲート絶縁層に対して浅いPN接合が維持される。
しかし、ある実施例では、第1半導体層102はシリコンから構成され、さらに、第2半導体層104は、ドープされたシリコン材料、シリコン/ゲルマニウム材料などのシリコンベースの材料であってもよい。他の実施形態では、半導体層102ならびに104は、結晶方向、材料組成など、少なくとも1つの特徴において異なっていてもよい。例えば、一実施形態では、第1半導体層102ならびに第2半導体層104は、異なる結晶方向を有するシリコンベースの層であってもよく、例えば、層102の方向は(110)または(100)であり、これに対して、層104の方向は(100)または(110)であってもよい。タイプの異なるトランジスタが形成され、電荷キャリア移動度がそれぞれの結晶方向に対して異なるアプリケーションにおいては、対応する配置が非常に有利となり得る。図2a〜2fに関連して、異なるトランジスタ型を使用した実施例を詳細に説明することにする。
Claims (12)
- 第1結晶半導体層(102、202)が形成された基板(101、201)と、
前記第1結晶半導体層(102、202)に形成された埋め込み絶縁層(103、203)と、
前記埋め込み絶縁層(103、203)に形成された第2結晶半導体層(104、204)と、
第1トランジスタ(100、200)と、を有し、この第1トランジスタは、前記第2結晶半導体層(104、204)の上方に形成された第1ゲート電極(105、205)と、前記第1結晶半導体層(102、202)内に延びている歪み半導体材料(112、212)を含む第1ドレイン及びソース領域(118、218)と、を含むものである、半導体デバイス。 - 前記第1結晶半導体層(102、202)は、少なくとも結晶方向および材料組成の一方が前記第2結晶半導体層(104、204)とは異なる、請求項1記載のデバイス。
- 前記歪み半導体材料(112、212)は、前記第2結晶半導体層(104、204)に圧縮歪みを生成するように選択され、前記第1結晶半導体層(102、202)は、(110)方向のシリコンを含む、請求項1記載のデバイス。
- 前記歪み半導体材料(112、212)は、前記第2結晶半導体層(104、204)に引っ張り歪みを生成するように選択され、前記第1結晶半導体層(102、202)は(100)方向のシリコンを含む、請求項1記載のデバイス。
- 前記ドレインならびにソース領域(118、218)は、隆起したドレインならびにソース領域である、請求項1記載のデバイス。
- 第2トランジスタ(200N)をさらに有し、この第2トランジスタ(200N)は、前記第1結晶半導体層(102、202)内に延びることなく前記第2結晶半導体層(104、204)に形成された第1ドレインならびにソース領域(218)を備える、請求項1記載のデバイス。
- 前記第1トランジスタ(100、200)はPチャネルトランジスタ(200P)であり、前記第1結晶半導体層(202)は(110)の方向を有しており、前記第2トランジスタはNチャネルトランジスタであり、前記第2結晶半導体層(204)は(100)の方向を有する、請求項6記載のデバイス。
- 前記第1トランジスタ(100、200)はNチャネルトランジスタであり、前記第1結晶半導体層は(100)の方向を有しており、前記第2トランジスタはPチャネルトランジスタであり、前記第2結晶半導体層は(110)の方向を有している、請求項6記載のデバイス。
- 第1トランジスタ(100、200)の第1ゲート電極(105、205)に隣接してリセス(111、211)を形成するステップを有し、前記第1ゲート電極(105、205)は、第1結晶半導体層(102、202)、前記第1結晶半導体層(102、202)に形成された埋め込み絶縁層(103、203)、および、前記埋め込み絶縁層(103、203)に形成された第2結晶半導体層(104、204)を含む基板(101、201)の上方に形成され、前記リセス(111、211)は、前記第1結晶半導体層(102、202)内に延びるものであり、更に、
前記リセス(111、211)に歪み半導体材料(112、212)をエピタキシャル成長させるステップを有する、方法。 - 前記歪み半導体材料(112、212)にドーパント種を注入することで、前記歪み半導体材料(112、212)にドレインならびにソース領域(118、218)を形成するステップをさらに含む、請求項9記載の方法。
- 第1チャンネル領域および第2チャンネル領域を画定するように、前記注入された種のドーパントプロファイルを調整するステップをさらに含み、前記第1チャネル領域は、ゲート絶縁層と前記第2半導体層の境界(121、221)に位置し、前記第2チャネル領域は、前記埋め込み絶縁層(103、203)と第2半導体層(104、204)の境界(114、214)に位置する、請求項10記載の方法。
- 前記リセス(111、211)のサイドウォールにサイドウォールスペーサ(113、213)を形成するステップをさらに含み、
前記歪み半導体材料(112、212)をエピタキシャル成長させるステップは、
前記歪み半導体材料(112、212)の第1部位(112A、212A)を成長させるステップと、
前記リセス(111、211)の前記サイドウォールスペーサ(113、213)の露出部位を除去するステップと、
前記エピタキシャル成長プロセスを継続するステップと、を含む請求項9記載の方法。
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DE102005052055A DE102005052055B3 (de) | 2005-10-31 | 2005-10-31 | Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben |
US11/466,572 US7399663B2 (en) | 2005-10-31 | 2006-08-23 | Embedded strain layer in thin SOI transistors and a method of forming the same |
PCT/US2006/041560 WO2007053382A1 (en) | 2005-10-31 | 2006-10-23 | An embedded strain layer in thin soi transistors and a method of forming the same |
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DE102005052055B3 (de) | 2007-04-26 |
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KR20080066834A (ko) | 2008-07-16 |
TW200729465A (en) | 2007-08-01 |
US20070096148A1 (en) | 2007-05-03 |
CN101300670A (zh) | 2008-11-05 |
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KR101290819B1 (ko) | 2013-07-30 |
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