JP2013069807A - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP2013069807A
JP2013069807A JP2011206549A JP2011206549A JP2013069807A JP 2013069807 A JP2013069807 A JP 2013069807A JP 2011206549 A JP2011206549 A JP 2011206549A JP 2011206549 A JP2011206549 A JP 2011206549A JP 2013069807 A JP2013069807 A JP 2013069807A
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Japan
Prior art keywords
insulating layer
semiconductor chip
layer
wiring
semiconductor
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JP2011206549A
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English (en)
Japanese (ja)
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JP2013069807A5 (enExample
Inventor
Kenta Uchiyama
健太 内山
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011206549A priority Critical patent/JP2013069807A/ja
Priority to US13/607,906 priority patent/US9136220B2/en
Publication of JP2013069807A publication Critical patent/JP2013069807A/ja
Publication of JP2013069807A5 publication Critical patent/JP2013069807A5/ja
Pending legal-status Critical Current

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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
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    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
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    • H10W72/071—Connecting or disconnecting
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    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W72/874—On different surfaces
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    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00—Package configurations
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
JP2011206549A 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法 Pending JP2013069807A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011206549A JP2013069807A (ja) 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法
US13/607,906 US9136220B2 (en) 2011-09-21 2012-09-10 Semiconductor package and method for manufacturing the semiconductor package

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Application Number Priority Date Filing Date Title
JP2011206549A JP2013069807A (ja) 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法

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JP2013069807A true JP2013069807A (ja) 2013-04-18
JP2013069807A5 JP2013069807A5 (enExample) 2014-09-04

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Cited By (3)

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JP2018085452A (ja) * 2016-11-24 2018-05-31 株式会社ジェイデバイス 半導体装置及びその製造方法
JP2021520652A (ja) * 2018-05-18 2021-08-19 ロジャーズ ジャーマニー ゲーエムベーハーＲｏｇｅｒｓ Ｇｅｒｍａｎｙ ＧｍｂＨ 電子モジュールとその製造方法
JP2023133675A (ja) * 2022-03-14 2023-09-27 住友電気工業株式会社 高周波装置の製造方法

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KR20150025129A (ko) * 2013-08-28 2015-03-10 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US20150279815A1 (en) * 2014-03-28 2015-10-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Having Conductive Columns
US10115648B2 (en) * 2015-11-23 2018-10-30 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package and electronic device including the same
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
TWI751331B (zh) * 2017-05-10 2022-01-01 日商三井化學股份有限公司 半導體裝置的製造方法以及半導體裝置的中間體
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging
US11101186B2 (en) * 2018-03-16 2021-08-24 Advanced Semiconductor Engineering, Inc. Substrate structure having pad portions
CN109801894A (zh) * 2018-12-28 2019-05-24 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法
US11257747B2 (en) * 2019-04-12 2022-02-22 Powertech Technology Inc. Semiconductor package with conductive via in encapsulation connecting to conductive element
US11139179B2 (en) * 2019-09-09 2021-10-05 Advanced Semiconductor Engineering, Inc. Embedded component package structure and manufacturing method thereof
US11365117B2 (en) 2019-12-23 2022-06-21 Industrial Technology Research Institute MEMS device and manufacturing method of the same
US11939212B2 (en) 2019-12-23 2024-03-26 Industrial Technology Research Institute MEMS device, manufacturing method of the same, and integrated MEMS module using the same
TWI819644B (zh) * 2022-06-07 2023-10-21 華東科技股份有限公司 增進打線接合承受力之晶片封裝的凸塊結構
CN116525474B (zh) * 2023-05-30 2026-07-21 江阴长电先进封装有限公司 封装结构及其形成方法

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JP2008300854A (ja) * 2008-07-02 2008-12-11 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2009038259A (ja) * 2007-08-02 2009-02-19 Sony Corp 半導体モジュール及びその製造方法
JP2010186847A (ja) * 2009-02-12 2010-08-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法、並びに電子装置
JP2011014944A (ja) * 2004-12-01 2011-01-20 Shinko Electric Ind Co Ltd 電子部品実装構造体の製造方法
JP2011018893A (ja) * 2009-07-08 2011-01-27 Samsung Electro-Mechanics Co Ltd 絶縁体、電子素子内蔵型印刷回路基板、及び電子素子内蔵型印刷回路基板の製造方法
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