JP5062248B2 - 磁気メモリチップ装置の製造方法 - Google Patents
磁気メモリチップ装置の製造方法 Download PDFInfo
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Description
12 チップ(磁気メモリチップ)
15 ダイアタッチフィルム
16 NiFe板(高透磁率板)
17,31 ダイアタッチフィルム(接着層)
21 ダイパッド(リードフレーム)
26 配線基板
本発明の実施の形態1に係る磁気メモリチップ装置の製造方法について図1に示すフローチャートを参照しながら説明する。まず、図2に示すように、シリコンからなるウェハ11(シリコンウェハ)上に複数のMRAMチップ(磁気メモリチップ)12を形成する(ステップS1)。MRAMチップは、基本的な構造として、磁性膜からなるピン(pin)層とフリー(free)層との間に極めて薄いトンネル絶縁層が設けられた磁気トンネル接合構造を備える。こうした磁気トンネル接合構造は、一般に、TMR(Tunneling Magneto Resistance)又はMTJ(Magnetic Tunnel Junction)と称される。
実施の形態2.
本発明の実施の形態2に係る磁気メモリチップ装置の製造方法について図16に示すフローチャートを参照しながら説明する。まず、実施の形態1と同様にステップS5までの工程を行う。次に、図17に示すようにウェハ11をダイアタッチフィルム31に貼り付け、ダイシングブレード18を用いてMRAMチップ12ごとにウェハ11をダイシングする(ステップS7)。その後、洗浄を行う。
実施の形態3.
本発明の実施の形態3に係る磁気メモリチップ装置の製造方法について図21に示すフローチャートを参照しながら説明する。まず、実施の形態1と同様にステップS5までの工程を行う。次に、MRAMチップ12ごとにウェハ11をダイシングし(ステップS7)、図22に示すようにMRAMチップ12を配線基板26上にダイボンドする(ステップS8)。なお、MRAMチップ12をリードフレーム上にダイボンドしてもよい。
Claims (3)
- 複数の磁気メモリチップが形成されたシリコンウェハを準備する工程と、
前記シリコンウェハの裏面を研削することにより前記シリコンウェハを所定の厚さまで薄くする工程と、
前記所定の厚さまで薄くされたシリコンウェハの裏面に、シリコンよりも透磁率が高い物質からなる高透磁率板を接着層を介して貼り付ける工程と、
前記高透磁率板を貼り付けた後に、前記シリコンウェハをダイシングすることによって、各々が前記高透磁率板をその裏面に有する複数の磁気メモリチップを形成する工程と、
を有する磁気メモリチップ装置の製造方法。 - 前記接着層はダイアタッチフィルムであり、前記ダイアタッチフィルムの厚さは10μm以上、40μm以下である請求項1に記載の磁気メモリチップ装置の製造方法。
- 前記高透磁率板の厚さは100μm以上であることを特徴とする請求項2に記載の磁気メモリチップ装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009501206A JP5062248B2 (ja) | 2007-02-27 | 2008-02-21 | 磁気メモリチップ装置の製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007047822 | 2007-02-27 | ||
JP2007047822 | 2007-02-27 | ||
PCT/JP2008/052976 WO2008105315A1 (ja) | 2007-02-27 | 2008-02-21 | 磁気メモリチップ装置の製造方法 |
JP2009501206A JP5062248B2 (ja) | 2007-02-27 | 2008-02-21 | 磁気メモリチップ装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2012166714A Division JP5626286B2 (ja) | 2007-02-27 | 2012-07-27 | 磁気メモリチップ装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JPWO2008105315A1 JPWO2008105315A1 (ja) | 2010-06-03 |
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JP5343261B2 (ja) * | 2008-11-18 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5425461B2 (ja) | 2008-12-26 | 2014-02-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5470602B2 (ja) * | 2009-04-01 | 2014-04-16 | ルネサスエレクトロニクス株式会社 | 磁気記憶装置 |
JP5483281B2 (ja) * | 2010-03-31 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置アセンブリ |
JP6144868B2 (ja) * | 2010-11-18 | 2017-06-07 | 日東電工株式会社 | フリップチップ型半導体裏面用フィルム、ダイシングテープ一体型半導体裏面用フィルム、及び、フリップチップ型半導体裏面用フィルムの製造方法 |
JP2013069807A (ja) * | 2011-09-21 | 2013-04-18 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法 |
US9385305B2 (en) * | 2013-02-19 | 2016-07-05 | Qualcomm Incorporated | STT-MRAM design enhanced by switching current induced magnetic field |
JP2013118407A (ja) * | 2013-03-06 | 2013-06-13 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2014112691A (ja) * | 2013-12-26 | 2014-06-19 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9269673B1 (en) * | 2014-10-22 | 2016-02-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages |
JP6280610B1 (ja) * | 2016-10-03 | 2018-02-14 | Tdk株式会社 | 磁気抵抗効果素子及びその製造方法、並びに位置検出装置 |
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US8124425B2 (en) | 2012-02-28 |
US20120122246A1 (en) | 2012-05-17 |
TWI509602B (zh) | 2015-11-21 |
TW200849243A (en) | 2008-12-16 |
US8524510B2 (en) | 2013-09-03 |
US20100120176A1 (en) | 2010-05-13 |
WO2008105315A1 (ja) | 2008-09-04 |
JP2012256906A (ja) | 2012-12-27 |
JP5626286B2 (ja) | 2014-11-19 |
JPWO2008105315A1 (ja) | 2010-06-03 |
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