JP2005340237A - 磁気記憶装置 - Google Patents
磁気記憶装置 Download PDFInfo
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- JP2005340237A JP2005340237A JP2004152886A JP2004152886A JP2005340237A JP 2005340237 A JP2005340237 A JP 2005340237A JP 2004152886 A JP2004152886 A JP 2004152886A JP 2004152886 A JP2004152886 A JP 2004152886A JP 2005340237 A JP2005340237 A JP 2005340237A
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- 238000003860 storage Methods 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 230000006870 function Effects 0.000 claims description 45
- 239000007769 metal material Substances 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 19
- 229910052748 manganese Inorganic materials 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 38
- 229910052710 silicon Inorganic materials 0.000 abstract description 38
- 239000010703 silicon Substances 0.000 abstract description 38
- 230000005389 magnetism Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 22
- 230000002238 attenuated effect Effects 0.000 description 9
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000035699 permeability Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000010953 base metal Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910018084 Al-Fe Inorganic materials 0.000 description 1
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910018192 Al—Fe Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910017566 Cu-Mn Inorganic materials 0.000 description 1
- 229910017827 Cu—Fe Inorganic materials 0.000 description 1
- 229910017871 Cu—Mn Inorganic materials 0.000 description 1
- 229910002551 Fe-Mn Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
【解決手段】 磁気記憶装置1は、ダイパッド3上に搭載されたシリコン基板5と、該シリコン基板5の主表面上に形成され磁気記憶素子を含む素子形成部6と、シリコン基板5を取り囲むモールドパッケージ2と、モールドパッケージ2に装着され磁場シールド機能を有する材料で少なくとも一部が構成されたリード4とを備える。
【選択図】 図1
Description
図1は、本発明の実施の形態1における磁気記憶装置を示す断面図である。図1に示す磁気記憶装置(MRAM)1は、MTJ(Magnet Tunnel Junction)素子あるいはTMR(Tunneling Magnetoresistive)素子などの磁気記憶素子を利用した不揮発性メモリである。
次に、図2および図3を用いて、本発明の実施の形態2およびその変形例について説明する。
次に、図4〜図6を用いて、本発明の実施の形態3およびその変形例について説明する。
次に、図7を用いて、本発明の実施の形態4について説明する。本実施の形態4では、磁気記憶装置の外装材の内部に装着された導体部に磁場シールド機能を付与している。
次に、図8を用いて、本発明の実施の形態5について説明する。本実施の形態5では、磁気記憶装置の外装材に装着され、その一部表面が外装材の表面に露出する導体部に、磁場シールド機能を付与している。本実施の形態5における導体部は、典型的には、基板における素子形成部の近傍に配置され、素子形成部で発生した熱を外部に放散する放熱部材(ヒートシンク)として使用することができる。
次に、図9を用いて、本発明の実施の形態6について説明する。本実施の形態6では、磁気記憶装置は、基板(チップ)を間に挟むように外装材に装着された複数の導体部を有し、各導体部に磁場シールド機能を付与している。
次に、図10を用いて、本発明の実施の形態7について説明する。本実施の形態7では、磁気記憶装置は、外装材の表面上に装着された導体部を有し、該導体部に磁場シールド機能を付与している。本実施の形態7の導体部も、典型的には、素子形成部で発生した熱を外部に放散する放熱部材(ヒートシンク)として使用することができる。
Claims (10)
- 基板と、
前記基板の主表面上に形成され、磁気記憶素子を含む素子形成部と、
前記基板を取り囲む外装材と、
前記外装材に装着され、磁場シールド機能を有する材料で少なくとも一部が構成された導体部と、
を備えた、磁気記憶装置。 - 前記導体部は、前記素子形成部と電気的に接続され前記外装材の内部から外部に延出するリードを含む、請求項1に記載の磁気記憶装置。
- 前記導体部は、前記基板を実装するダイパッドを含む、請求項1または請求項2に記載の磁気記憶装置。
- 前記導体部は、前記素子形成部で発生した熱を外部に放散するヒートシンクを含む、請求項1から請求項3のいずれかに記載の磁気記憶装置。
- 前記導体部の少なくとも一部を、Mn、FeおよびCuからなる群から選ばれる少なくとも1種の材料を含む金属材料で構成した、請求項1から請求項4のいずれかに記載の磁気記憶装置。
- 基板と、
前記基板の主表面上に形成され、磁気記憶素子を含む素子形成部と、
前記基板の内部に形成され、磁場シールド機能を有する材料を含む導電性の磁場シールド部と、
を備えた、磁気記憶装置。 - 前記素子形成部は、磁気記憶素子が形成されるセルアレイ部と、前記磁気記憶素子の動作制御を行う周辺回路が形成される周辺回路部とを含み、
前記セルアレイ部直下に位置する前記基板内に前記磁場シールド部を形成する一方で、前記周辺回路部直下に位置する前記基板内には前記磁場シールド部を形成しないようにした、請求項6に記載の磁気記憶装置。 - 前記磁場シールド部は、Mn、FeおよびCuからなる群から選ばれる少なくとも1種の材料を含む、請求項6または請求項7に記載の磁気記憶装置。
- 基板と、
前記基板の主表面上に形成され、磁気記憶素子と配線とを含む素子形成部とを備え、
磁場シールド機能を有する材料で前記配線を構成するとともに、前記磁気記憶素子の形成領域全体を覆うように前記配線を配置した、磁気記憶装置。 - 前記配線を、Mn、FeおよびCuからなる群から選ばれる少なくとも1種の材料を含む金属材料で構成した、請求項9に記載の磁気記憶装置。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008105315A1 (ja) * | 2007-02-27 | 2008-09-04 | Renesas Technology Corp. | 磁気メモリチップ装置の製造方法 |
JP2010245106A (ja) * | 2009-04-01 | 2010-10-28 | Renesas Electronics Corp | 磁気記憶装置 |
JP2013145844A (ja) * | 2012-01-16 | 2013-07-25 | Dainippon Printing Co Ltd | 半導体装置 |
-
2004
- 2004-05-24 JP JP2004152886A patent/JP2005340237A/ja active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008105315A1 (ja) * | 2007-02-27 | 2008-09-04 | Renesas Technology Corp. | 磁気メモリチップ装置の製造方法 |
US8124425B2 (en) | 2007-02-27 | 2012-02-28 | Renesas Electronics Corporation | Method for manufacturing magnetic memory chip device |
JP2012256906A (ja) * | 2007-02-27 | 2012-12-27 | Renesas Electronics Corp | 磁気メモリチップを有する半導体装置の製造方法 |
US8524510B2 (en) | 2007-02-27 | 2013-09-03 | Renesas Electronics Corporation | Method for manufacturing magnetic memory chip device |
JP2010245106A (ja) * | 2009-04-01 | 2010-10-28 | Renesas Electronics Corp | 磁気記憶装置 |
US8492881B2 (en) | 2009-04-01 | 2013-07-23 | Renesas Electronics Corporation | Magnetic storage device |
JP2013145844A (ja) * | 2012-01-16 | 2013-07-25 | Dainippon Printing Co Ltd | 半導体装置 |
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