JP2007318045A - 半導体装置及び半導体パッケージ - Google Patents
半導体装置及び半導体パッケージ Download PDFInfo
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- JP2007318045A JP2007318045A JP2006148786A JP2006148786A JP2007318045A JP 2007318045 A JP2007318045 A JP 2007318045A JP 2006148786 A JP2006148786 A JP 2006148786A JP 2006148786 A JP2006148786 A JP 2006148786A JP 2007318045 A JP2007318045 A JP 2007318045A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】インダクタと抵抗器とを有する遮蔽構造8Aが、半導体チップ1に形成された回路2に対向して設けられた半導体装置51により、上記課題を解決する。このとき、遮蔽構造8Aは、インダクタと抵抗器とからなる微小ループを複数個有し、かつ、半導体チップ1に形成された回路2とは電気的に絶縁している構成とすることができる。本発明の半導体パッケージ101は、少なくとも1つ以上の上記半導体装置51がインターポーザ基板4に搭載されている。
【選択図】図1
Description
2,2A,2B 回路
3 ワイヤ
4 インターポーザ基板
5 接着層
6 バンプ
7 樹脂
8,8’,8A,8B,8C 遮蔽構造
10 絶縁層
10A,10B 絶縁フィルム
11 抵抗器
12 インダクタ
13,14,14A,14B 抵抗器
15 インダクタ
15A,15B 平行配線
16A,16B 端子
20 微小ループ
51,52,53,54A,54B,55A,55B,57,58 半導体装置
101,102,103,104,105,106 半導体パッケージ
Claims (14)
- インダクタと抵抗器とを有する遮蔽構造が、半導体チップに形成された回路に対向して設けられていることを特徴とする半導体装置。
- 前記遮蔽構造は、前記インダクタと前記抵抗器とからなる微小ループを複数個有し、かつ、前記半導体チップに形成された回路とは電気的に絶縁していることを特徴とする請求項1に記載の半導体装置。
- 前記遮蔽構造は、前記インダクタの両端が前記抵抗器を介して接地している回路構造を複数個有することを特徴とする請求項1に記載の半導体装置。
- 前記遮蔽構造を構成するインダクタが、前記半導体チップに形成された回路の再配線層に形成されていることを特徴とする請求項1〜3のいずれかに記載の半導体装置。
- 前記遮蔽構造を構成するインダクタが絶縁層内に形成され、当該絶縁層が前記半導体チップの回路に対向して設けられていることを特徴とする請求項1〜3のいずれかに記載の半導体装置。
- 前記遮蔽構造を構成するインダクタと抵抗器がシリコン薄片に形成され、当該シリコン薄片が前記半導体チップの回路に対向して設けられていることを特徴とする請求項1〜3のいずれかに記載の半導体装置。
- 前記シリコン薄片がドーピングされていることを特徴とする請求項6に記載の半導体装置。
- 前記インダクタが、円形状、渦巻き形状及び線分のうちのいずれかであることを特徴とする請求項1〜7のいずれかに記載の半導体装置。
- 前記インダクタが複数層にわたって形成されていることを特徴とする請求項1〜8のいずれかに記載の半導体装置。
- 前記抵抗器が、薄膜抵抗器、チップ抵抗器、及び前記電子回路の一部に形成された抵抗のうちのいずれかであることを特徴とする請求項1〜9のいずれかに記載の半導体装置。
- 請求項1〜10のいずれかに記載の半導体装置が少なくとも1つ以上、インターポーザ基板に搭載されていることを特徴とする半導体パッケージ。
- 前記半導体装置と前記インターポーザ基板とがワイヤボンディングされていることを特徴とする請求項11に記載の半導体パッケージ。
- 前記半導体装置と前記インターポーザ基板とがフリップチップ接続されていることを特徴とする請求項11に記載の半導体パッケージ。
- 請求項11に記載の半導体パッケージにおいて、前記半導体装置内のインダクタが、前記インターポーザ基板の配線層に形成されていることを特徴とする半導体パッケージ。
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JP2006148786A JP2007318045A (ja) | 2006-05-29 | 2006-05-29 | 半導体装置及び半導体パッケージ |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008182207A (ja) * | 2006-12-28 | 2008-08-07 | Sanyo Electric Co Ltd | 半導体モジュールおよび携帯機器 |
JP2012033860A (ja) * | 2010-08-02 | 2012-02-16 | Headway Technologies Inc | 積層半導体基板および積層チップパッケージ並びにこれらの製造方法 |
JP2012033861A (ja) * | 2010-08-02 | 2012-02-16 | Headway Technologies Inc | 積層半導体基板および積層チップパッケージ並びにこれらの製造方法 |
JP2014120602A (ja) * | 2012-12-17 | 2014-06-30 | Denso Corp | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63119248U (ja) * | 1987-01-29 | 1988-08-02 | ||
JP2002271088A (ja) * | 2001-03-07 | 2002-09-20 | Mitsubishi Electric Corp | 不要輻射抑制システム |
-
2006
- 2006-05-29 JP JP2006148786A patent/JP2007318045A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63119248U (ja) * | 1987-01-29 | 1988-08-02 | ||
JP2002271088A (ja) * | 2001-03-07 | 2002-09-20 | Mitsubishi Electric Corp | 不要輻射抑制システム |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008182207A (ja) * | 2006-12-28 | 2008-08-07 | Sanyo Electric Co Ltd | 半導体モジュールおよび携帯機器 |
JP2012033860A (ja) * | 2010-08-02 | 2012-02-16 | Headway Technologies Inc | 積層半導体基板および積層チップパッケージ並びにこれらの製造方法 |
JP2012033861A (ja) * | 2010-08-02 | 2012-02-16 | Headway Technologies Inc | 積層半導体基板および積層チップパッケージ並びにこれらの製造方法 |
JP2014120602A (ja) * | 2012-12-17 | 2014-06-30 | Denso Corp | 半導体装置 |
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