JP4595593B2 - 半導体ic内蔵基板 - Google Patents
半導体ic内蔵基板 Download PDFInfo
- Publication number
- JP4595593B2 JP4595593B2 JP2005063288A JP2005063288A JP4595593B2 JP 4595593 B2 JP4595593 B2 JP 4595593B2 JP 2005063288 A JP2005063288 A JP 2005063288A JP 2005063288 A JP2005063288 A JP 2005063288A JP 4595593 B2 JP4595593 B2 JP 4595593B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate according
- substrate
- embedded substrate
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
110 多層基板
110a 多層基板の一方の表面(端子面)
110b 多層基板の他方の表面
111〜113,201,202 樹脂層
121 信号端子電極
122 グランド端子電極
130 半導体IC
130a 半導体ICの主面
130a 半導体ICの裏面
131 ランド電極
132 スタッドバンプ
140 放熱層
140 切り欠き
141,143 スルーホール電極
142 内部配線パターン
150 電極パターン
211,212 容量電極
310 デカップリングコンデンサ
311 デカップリングコンデンサの一方の端子
312 デカップリングコンデンサの他方の端子
320 コイル部品
330 フィルタ部品
A 有効領域
P スルーホール電極の配列ピッチ
Claims (18)
- 積層された複数の絶縁層からなり、一方の表面に複数の端子電極が形成された多層基板と、
主面が前記多層基板の前記一方の表面側を向くよう、前記多層基板に内蔵された半導体ICと、
前記半導体ICの裏面の少なくとも一部に接して設けられた放熱層と、
前記多層基板を貫通して設けられ、前記放熱層と前記端子電極とを接続するスルーホール電極とを備え、
前記複数の絶縁層のうち、前記半導体ICから見て前記端子電極とは反対側に位置する第2の絶縁層は、前記半導体ICの前記裏面の外周部分を覆っており、
前記放熱層は、前記半導体ICの前記裏面のうち、前記第2の絶縁層に覆われていない領域の実質的に全面に接して設けられていることを特徴とする半導体IC内蔵基板。 - 前記放熱層は、前記多層基板の他方の表面のほぼ全面を覆うように形成されていることを特徴とする請求項1に記載の半導体IC内蔵基板。
- 前記スルーホール電極は、前記半導体ICを取り囲むように複数設けられていることを特徴とする請求項1又は2に記載の半導体IC内蔵基板。
- 前記複数のスルーホール電極の配列ピッチは、前記半導体ICの動作周波数の逆数をλとした場合、λ/4以下に設定されていることを特徴とする請求項3に記載の半導体IC内蔵基板。
- 前記放熱層がメッキにより形成されていることを特徴とする請求項2乃至4のいずれか1項に記載の半導体IC内蔵基板。
- 前記半導体ICの前記裏面の粗さ(Ra)が1μm以上であることを特徴とする請求項1乃至5のいずれか1項に記載の半導体IC内蔵基板。
- 前記半導体ICが薄膜化されていることを特徴とする請求項1乃至6のいずれか1項に記載の半導体IC内蔵基板。
- 前記複数の絶縁層のうち、最も前記端子電極側に位置する第1の絶縁層は、フィラーを実質的に含まない樹脂によって構成されていることを特徴とする請求項1乃至7のいずれか1項に記載の半導体IC内蔵基板。
- 前記第2の絶縁層の熱膨張係数は、前記半導体ICの熱膨張係数とほぼ等しいことを特徴とする請求項1乃至8のいずれか1項に記載の半導体IC内蔵基板。
- 前記複数の絶縁層に含まれる第3の絶縁層を介して形成された、コンデンサを構成する一対の容量電極をさらに備えることを特徴とする請求項1乃至9のいずれか1項に記載の半導体IC内蔵基板。
- 前記第3の絶縁層は、他の絶縁層の少なくとも一つよりも誘電率が高いことを特徴とする請求項10に記載の半導体IC内蔵基板。
- 前記第3の絶縁層は、他の絶縁層の少なくとも一つよりも薄いことを特徴とする請求項10又は11に記載の半導体IC内蔵基板。
- 前記第3の絶縁層及び前記一対の容量電極により構成されるコンデンサがデカップリングコンデンサであることを特徴とする請求項10乃至12のいずれか1項に記載の半導体IC内蔵基板。
- それぞれインダクタ及び抵抗素子として機能する複数の内部配線パターンをさらに備え、前記一対の容量電極により形成されるコンデンサと前記インダクタ及び前記抵抗素子によって、LCRフィルタが構成されていることを特徴とする請求項10乃至13のいずれか1項に記載の半導体IC内蔵基板。
- 前記多層基板の他方の表面側に搭載されたチップ部品をさらに備えることを特徴とする請求項1乃至14のいずれか1項に記載の半導体IC内蔵基板。
- 前記チップ部品は、前記多層基板の前記他方の表面の周辺領域に搭載されていることを特徴とする請求項15に記載の半導体IC内蔵基板。
- 前記放熱層には切り欠きが形成されており、前記チップ部品の少なくとも一部の端子は、前記切り欠きに囲まれるように設けられた電極パターンに接続されていることを特徴とする請求項15に記載の半導体IC内蔵基板。
- 前記チップ部品は、コンデンサ部品、コイル部品及びフィルタ部品からなる群より選ばれた少なくとも一つの部品を含んでいることを特徴とする請求項15乃至17のいずれか1項に記載の半導体IC内蔵基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005063288A JP4595593B2 (ja) | 2005-03-08 | 2005-03-08 | 半導体ic内蔵基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005063288A JP4595593B2 (ja) | 2005-03-08 | 2005-03-08 | 半導体ic内蔵基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006253168A JP2006253168A (ja) | 2006-09-21 |
JP4595593B2 true JP4595593B2 (ja) | 2010-12-08 |
Family
ID=37093366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005063288A Active JP4595593B2 (ja) | 2005-03-08 | 2005-03-08 | 半導体ic内蔵基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4595593B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5046720B2 (ja) * | 2006-12-22 | 2012-10-10 | 京セラ株式会社 | コイル内蔵基板 |
KR100867150B1 (ko) * | 2007-09-28 | 2008-11-06 | 삼성전기주식회사 | 칩 캐패시터가 내장된 인쇄회로기판 및 칩 캐패시터의 내장방법 |
US7989942B2 (en) * | 2009-01-20 | 2011-08-02 | Altera Corporation | IC package with capacitors disposed on an interposal layer |
JP2012009828A (ja) * | 2010-05-26 | 2012-01-12 | Jtekt Corp | 多層回路基板 |
JP2014175589A (ja) * | 2013-03-12 | 2014-09-22 | Denso Corp | プリント配線基板および電子回路装置 |
US20170053884A1 (en) * | 2015-08-17 | 2017-02-23 | Mediatek Inc. | Structure and layout of ball grid array packages |
CN208938956U (zh) * | 2017-11-07 | 2019-06-04 | 台湾东电化股份有限公司 | 基板结构 |
US10811332B2 (en) | 2017-11-07 | 2020-10-20 | Tdk Taiwan Corp. | Thermal-dissipating substrate structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001358259A (ja) * | 2000-06-15 | 2001-12-26 | Seiko Epson Corp | 半導体パッケージ |
JP2003152131A (ja) * | 2001-08-31 | 2003-05-23 | Mitsubishi Electric Corp | 中空封着パッケージおよびその製造方法 |
JP2003347485A (ja) * | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
JP2004128029A (ja) * | 2002-09-30 | 2004-04-22 | Sony Corp | 高周波モジュール装置の製造方法。 |
-
2005
- 2005-03-08 JP JP2005063288A patent/JP4595593B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001358259A (ja) * | 2000-06-15 | 2001-12-26 | Seiko Epson Corp | 半導体パッケージ |
JP2003152131A (ja) * | 2001-08-31 | 2003-05-23 | Mitsubishi Electric Corp | 中空封着パッケージおよびその製造方法 |
JP2003347485A (ja) * | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
JP2004128029A (ja) * | 2002-09-30 | 2004-04-22 | Sony Corp | 高周波モジュール装置の製造方法。 |
Also Published As
Publication number | Publication date |
---|---|
JP2006253168A (ja) | 2006-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20200373079A1 (en) | Inductor component and inductor-component incorporating substrate | |
CN109427461B (zh) | 电感器部件 | |
US11682517B2 (en) | Inductor component | |
JP4595593B2 (ja) | 半導体ic内蔵基板 | |
US8779299B2 (en) | Electronic component-embeded board and method for manufacturing the same | |
US8018311B2 (en) | Microminiature power converter | |
US10952326B2 (en) | Printed wiring board and switching regulator | |
WO2010041630A1 (ja) | 半導体装置及びその製造方法 | |
US9847299B2 (en) | Semiconductor package and mounting structure thereof | |
US9313911B2 (en) | Package substrate | |
US11399438B2 (en) | Power module, chip-embedded package module and manufacturing method of chip-embedded package module | |
JP2002083925A (ja) | 集積回路装置 | |
KR20080029908A (ko) | 반도체 내장 기판 및 그 제조 방법 | |
US10917974B2 (en) | Circuit board incorporating electronic component and manufacturing method thereof | |
JP2005223223A (ja) | 半導体ic内蔵基板及びその製造方法、並びに、半導体ic内蔵モジュール | |
US20050012192A1 (en) | Hybrid integrated circuit | |
JP2006019342A (ja) | 半導体ic内蔵基板 | |
JP4457779B2 (ja) | 半導体ic内蔵基板 | |
JP2006019340A (ja) | 半導体ic内蔵基板 | |
JP2018006437A (ja) | 複合デバイス | |
JP2009267267A (ja) | 電子部品搭載装置 | |
JP4213529B2 (ja) | 積層モジュール基板及びその製造方法並びに半導体ic搭載モジュール | |
US20150282315A1 (en) | Printed circuit board and method of manufacturing the same | |
JP2009231480A (ja) | 半導体装置 | |
TW200527616A (en) | Stacked type semiconductor encapsulation device having protection mask |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071228 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100608 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100805 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100824 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100906 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4595593 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131001 Year of fee payment: 3 |