JP2012513621A5 - - Google Patents

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Publication number
JP2012513621A5
JP2012513621A5 JP2011543475A JP2011543475A JP2012513621A5 JP 2012513621 A5 JP2012513621 A5 JP 2012513621A5 JP 2011543475 A JP2011543475 A JP 2011543475A JP 2011543475 A JP2011543475 A JP 2011543475A JP 2012513621 A5 JP2012513621 A5 JP 2012513621A5
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Japan
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layer
insulating
conductive
layers
wafer
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JP2011543475A
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English (en)
Japanese (ja)
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JP2012513621A (ja
JP5701772B2 (ja
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Priority claimed from SE0802663A external-priority patent/SE533992C2/sv
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JP2011543475A 2008-12-23 2009-12-23 ビア構造及びその製造方法 Active JP5701772B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE0802663A SE533992C2 (sv) 2008-12-23 2008-12-23 Elektrisk anslutning i en struktur med isolerande och ledande lager
SE0802663-5 2008-12-23
PCT/SE2009/051496 WO2010074649A1 (en) 2008-12-23 2009-12-23 Via structure and method thereof

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2015029296A Division JP2015146018A (ja) 2008-12-23 2015-02-18 偏向可能マイクロミラーを含むデバイス
JP2015029295A Division JP6093788B2 (ja) 2008-12-23 2015-02-18 デバイスを作る方法、半導体デバイス及び前駆構造物

Publications (3)

Publication Number Publication Date
JP2012513621A JP2012513621A (ja) 2012-06-14
JP2012513621A5 true JP2012513621A5 (enExample) 2013-02-14
JP5701772B2 JP5701772B2 (ja) 2015-04-15

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ID=42288012

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2011543475A Active JP5701772B2 (ja) 2008-12-23 2009-12-23 ビア構造及びその製造方法
JP2015029295A Active JP6093788B2 (ja) 2008-12-23 2015-02-18 デバイスを作る方法、半導体デバイス及び前駆構造物
JP2015029296A Pending JP2015146018A (ja) 2008-12-23 2015-02-18 偏向可能マイクロミラーを含むデバイス

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2015029295A Active JP6093788B2 (ja) 2008-12-23 2015-02-18 デバイスを作る方法、半導体デバイス及び前駆構造物
JP2015029296A Pending JP2015146018A (ja) 2008-12-23 2015-02-18 偏向可能マイクロミラーを含むデバイス

Country Status (7)

Country Link
US (2) US8592981B2 (enExample)
EP (3) EP2377154B1 (enExample)
JP (3) JP5701772B2 (enExample)
KR (2) KR101710334B1 (enExample)
CN (1) CN102362346B (enExample)
SE (1) SE533992C2 (enExample)
WO (1) WO2010074649A1 (enExample)

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CN106783801B (zh) * 2016-11-18 2020-02-14 浙江大学 高密度soi封装基板及其制备方法
US10204873B2 (en) * 2017-05-08 2019-02-12 Infineon Technologies Americas Corp. Breakable substrate for semiconductor die
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