WO2007137729A3 - Verfahren zur herstellung einer halbleiteranordnung mit isolationsstruktur, halbleiteranordnung und deren verwendung - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mit isolationsstruktur, halbleiteranordnung und deren verwendung Download PDF

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Publication number
WO2007137729A3
WO2007137729A3 PCT/EP2007/004506 EP2007004506W WO2007137729A3 WO 2007137729 A3 WO2007137729 A3 WO 2007137729A3 EP 2007004506 W EP2007004506 W EP 2007004506W WO 2007137729 A3 WO2007137729 A3 WO 2007137729A3
Authority
WO
WIPO (PCT)
Prior art keywords
region
semiconductor array
insulation structure
production
semiconductor
Prior art date
Application number
PCT/EP2007/004506
Other languages
English (en)
French (fr)
Other versions
WO2007137729A2 (de
Inventor
Juergen Berntgen
Frank Dietz
Michael Graf
Stefan Schwantes
Original Assignee
Atmel Germany Gmbh
Juergen Berntgen
Frank Dietz
Michael Graf
Stefan Schwantes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Germany Gmbh, Juergen Berntgen, Frank Dietz, Michael Graf, Stefan Schwantes filed Critical Atmel Germany Gmbh
Publication of WO2007137729A2 publication Critical patent/WO2007137729A2/de
Publication of WO2007137729A3 publication Critical patent/WO2007137729A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Halbleiteranordnung für einen integrierten Schaltkreis - mit einem ersten Bereich (10) in dem eine Anzahl von Bauelementen ausgebildet ist, mit einem zweiten Bereich (60), - mit einer vergrabenen Isolatorschicht (50, SOI) zur vertikalen Isolation des ersten Bereichs (10), - mit einer Isolationsstruktur (1 ), die zwischen dem ersten Bereich (10) und dem zweiten Bereich (60) zur lateralen Isolation des ersten Bereichs (10) vom zweiten Bereich (60) ausgebildet ist, bei der - die Isolationsstruktur (1 ) eine Grabenstruktur (20, 21, 22, 23, 29) mit einem Dielektrikum und eine Leiterstruktur (30, 31, 32, 33, 39) mit einem Halbleitermaterial aufweist, - die Grabenstruktur (20, 21, 22, 23, 29) an die vergrabene Isolatorschicht (50, SOI) grenzt, und - die Leiterstruktur (30, 31, 32, 33, 39) zur leitenden Verbindung des ersten Bereichs (10) mit dem zweiten Bereich (60) ausgebildet ist.
PCT/EP2007/004506 2006-05-26 2007-05-22 Verfahren zur herstellung einer halbleiteranordnung mit isolationsstruktur, halbleiteranordnung und deren verwendung WO2007137729A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006024495A DE102006024495A1 (de) 2006-05-26 2006-05-26 Verfahren zur Herstellung einer Halbleiteranordnung, Halbleiteranordnung und deren Verwendung
DE102006024495.8 2006-05-26

Publications (2)

Publication Number Publication Date
WO2007137729A2 WO2007137729A2 (de) 2007-12-06
WO2007137729A3 true WO2007137729A3 (de) 2008-03-27

Family

ID=38622197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2007/004506 WO2007137729A2 (de) 2006-05-26 2007-05-22 Verfahren zur herstellung einer halbleiteranordnung mit isolationsstruktur, halbleiteranordnung und deren verwendung

Country Status (3)

Country Link
US (1) US20070290226A1 (de)
DE (1) DE102006024495A1 (de)
WO (1) WO2007137729A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8466492B1 (en) * 2012-01-31 2013-06-18 Infineon Technologies Austria Ag Semiconductor device with edge termination structure
US8994117B2 (en) 2012-12-18 2015-03-31 International Business Machines Corporation Moat construction to reduce noise coupling to a quiet supply

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1180800A2 (de) * 2000-08-14 2002-02-20 Hitachi, Ltd. Integriertes Halbleiterschaltkreisbauelement und dessen Herstellungsverfahren
US6355537B1 (en) * 1999-02-23 2002-03-12 Silicon Wave, Inc. Method of providing radio frequency isolation of device mesas using guard ring regions within an integrated circuit device
US20030119229A1 (en) * 2001-12-26 2003-06-26 Roh Tae Moon Method for fabricating a high-voltage high-power integrated circuit device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507158A (en) * 1983-08-12 1985-03-26 Hewlett-Packard Co. Trench isolated transistors in semiconductor films
US4593458A (en) * 1984-11-02 1986-06-10 General Electric Company Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices
JP3575908B2 (ja) * 1996-03-28 2004-10-13 株式会社東芝 半導体装置
CA2242846A1 (en) * 1998-07-09 2000-01-09 Newbridge Networks Corporation Radio interface card for a broadband wireless atm system
JP2005268336A (ja) * 2004-03-16 2005-09-29 Nec Electronics Corp 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355537B1 (en) * 1999-02-23 2002-03-12 Silicon Wave, Inc. Method of providing radio frequency isolation of device mesas using guard ring regions within an integrated circuit device
EP1180800A2 (de) * 2000-08-14 2002-02-20 Hitachi, Ltd. Integriertes Halbleiterschaltkreisbauelement und dessen Herstellungsverfahren
US20030119229A1 (en) * 2001-12-26 2003-06-26 Roh Tae Moon Method for fabricating a high-voltage high-power integrated circuit device

Also Published As

Publication number Publication date
US20070290226A1 (en) 2007-12-20
WO2007137729A2 (de) 2007-12-06
DE102006024495A1 (de) 2007-11-29

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