CN103460377B - 高频封装 - Google Patents

高频封装 Download PDF

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CN103460377B
CN103460377B CN201280017668.6A CN201280017668A CN103460377B CN 103460377 B CN103460377 B CN 103460377B CN 201280017668 A CN201280017668 A CN 201280017668A CN 103460377 B CN103460377 B CN 103460377B
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base plate
dielectric base
conductor
frequency component
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CN103460377A (zh
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橘川雄亮
铃木拓也
海野友幸
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007Casings
    • H05K9/006Casings specially adapted for signal processing applications, e.g. CATV, tuner, antennas amplifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Power Engineering (AREA)
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Abstract

实施方式的高频封装(100)具备:第一电介质基板(10),在背面设置有信号布线和接地导体(30);高频元件(20),经由第一连接导体(40)连接在第一电介质基板的背面;第二电介质基板(11),在夹着所述高频元件与所述背面对置的表面设置有信号布线和接地导体(30);多个第二连接导体(41),以包围所述高频元件的方式配置,连接第一电介质基板的背面的接地导体和第二电介质基板的表面的接地导体。实施方式的高频封装(100)在所述第二电介质基板的表面的高频元件的下部形成有被导体图案包围的电介质空间(60)。

Description

高频封装
技术领域
本发明涉及高频封装。
背景技术
以往的高频封装的结构例如像专利文献1所公开的那样,由在背面表层具有信号布线和接地导体的第一电介质基板、在第一电介质基板的背面表层安装的高频元件、在表面表层具有信号布线和接地导体的第二电介质基板、连接导体构成,高频元件安装在第一电介质基板的背面表层,以用第一电介质基板的背面表层和第二电介质基板的表面表层夹着高频元件的方式构成,连接导体以包围高频元件的方式连接在第一与第二电介质基板的接地导体之间,具有屏蔽空间。
现有技术文献
专利文献
专利文献1:国际公开第2010/026990号。
发明内容
发明要解决的课题
然而,根据上述现有技术,在高频元件的一个边的尺寸变成接近基频的1/2波长的大小的情况下,会在基频附近产生空腔谐振频率。因此,在高频元件为有源元件的情况下,不能确保端子间的隔离度(isolation),存在产生振荡的问题。
本发明是鉴于上述情形而做成的,其目的在于得到改善了端子间的隔离度的高频封装。
用于解决课题的方案
为了解决上述的课题并达到目的,本发明的特征在于,具备:第一电介质基板,在背面设置有信号布线和接地导体;高频元件,经由第一连接导体连接在第一电介质基板的背面;第二电介质基板,在夹着所述高频元件与所述背面对置的表面设置有信号布线和接地导体;多个第二连接导体,以包围所述高频元件的方式配置,连接第一电介质基板的背面的接地导体与第二电介质基板的表面的接地导体,在所述第二电介质基板的表面的高频元件的下部形成有被导体图案包围的电介质空间。
发明效果
根据本发明,起到得到改善了端子间的隔离度的高频封装的效果。
附图说明
图1是示出本发明的实施方式1的高频封装的电路结构的图。
图2是示出本发明的实施方式2的高频封装的电路结构的图。
图3-1是示出没有电介质空间的情况下的端子间隔离度的计算结果的图。
图3-2是示出本发明的实施方式1的有电介质空间的情况下的端子间隔离度的计算结果的图。
具体实施方式
以下,基于附图详细地说明本发明的高频封装的实施方式。另外,本发明并不被该实施方式限定。
实施方式1
图1是示出本发明的实施方式1的高频封装100的电路结构的图。高频封装100具备:第一电介质基板10,在背面表层具有信号布线和接地导体;高频元件20,隔着连接导体40安装于第一电介质基板10;第二电介质基板11,在表面表层具有信号布线和接地导体30,并且具有周围被由导体构成的通路(via)50以及内层图案51包围而构成的电介质空间60;作为连接导体的焊料球41,将第一电介质基板10与第二电介质基板11的接地导体30之间连接。
对实施方式1的高频封装100的动作进行说明。高频元件20隔着连接导体40安装于第一电介质基板10。此外,高频元件20以被第一电介质基板10与第二电介质基板11夹着的方式被包围,进而,焊料球41以包围高频元件20的方式连接第一电介质基板10与第二电介质基板11的接地导体30之间,具有屏蔽空间。
此处,在第二电介质基板11的高频元件20的下部构成有被作为导体的通路50以及内层图案51包围而构成的电介质空间60。因此,屏蔽空间内的有效的介电常数增大了电介质空间60的介电常数的量,空腔谐振频率向低的频率偏移,由此,改善端子间的隔离度。
在图3-1中示出没有电介质空间的情况下的端子间隔离度的计算结果,在图3-2中示出有电介质空间的情况下的端子间隔离度的计算结果。通过对图3-1和图3-2进行比较可知,由于本实施方式的电介质空间的存在而改善了端子间隔离度。
实施方式2
图2是示出本发明的实施方式2的高频封装200的电路结构的图。高频封装200具备:第一电介质基板10,在背面表层具有信号布线和接地导体;高频元件20,隔着连接导体40安装于第一电介质基板10;第二电介质基板11,在表面表层具有信号布线和接地导体30,并且具有周围被由导体构成的通路50以及内层图案51包围的空腔空间70;作为连接导体的焊料球41,将第一电介质基板10与第二电介质基板11的接地导体30之间连接。
对实施方式2的高频封装200的动作进行说明。高频元件20隔着连接导体40安装于第一电介质基板10。此外,高频元件20以被第一电介质基板10与第二电介质基板11夹着的方式被包围,进而,焊料球41以包围高频元件20的方式连接第一电介质基板10与第二电介质基板11的接地导体30之间,具有屏蔽空间。
此处,在第二电介质基板11的高频元件20的下部构成有被作为导体的通路50以及内层图案51包围的空腔空间70。因此,屏蔽空间内的有效的介电常数减小了空腔空间70的介电常数的量,空腔谐振频率向高的频率偏移,由此,改善了端子间的隔离度。
进而,本申请发明不被上述实施方式限定,在实施阶段,能在不脱离其宗旨的范围内进行各种变形。此外,在上述实施方式中包括各种阶段的发明,通过所公开的多个构成要件中的适当的组合能提出各种发明。
例如,在即使从上述实施方式1以及2分别示出的全部构成要件中删除几个构成要件,也能解决在发明要解决的课题一栏中叙述的课题并得到在发明效果一栏中叙述的效果的情况下,删除了该构成要件的结构能作为发明被提出。进而,也可以适当地组合上述实施方式1以及2的构成要件。
产业上的可利用性
如上所述,本发明的高频封装对端子间的隔离度是有用的,特别是,适合高频元件是有源元件的情况。
附图标记说明
10:第一电介质基板;
11:第二电介质基板;
20:高频元件;
30:接地导体;
40:连接导体;
41:焊料球;
50:通路;
51:内层图案;
60:电介质空间;
70:空腔空间;
100、200:高频封装。

Claims (1)

1.一种高频封装,其特征在于,具备:
第一电介质基板,在背面表层设置有信号布线和第一接地导体;
高频元件,经由第一连接导体连接在所述第一电介质基板的所述背面;
第二电介质基板,在夹着所述高频元件以及屏蔽空间与所述背面对置的表面形成的空腔周围的表层上设置有信号布线和第二接地导体;以及
多个第二连接导体,以经由所述屏蔽空间包围所述高频元件的方式连接所述第一接地导体与所述第二接地导体,
所述空腔的底面与所述高频元件相对,并铺设有导体图案,所述空腔的内部空间作为用于使所述屏蔽空间的空腔谐振频率偏移的空腔空间,
所述导体图案经由设置在所述空腔的内侧侧壁上的通路导体连接到所述第二接地导体,
所述空腔被所述导体图案以及所述通路导体覆盖,
所述空腔空间用于使所述空腔谐振频率向更高的频率偏移。
CN201280017668.6A 2011-04-14 2012-01-31 高频封装 Active CN103460377B (zh)

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EP2698819A1 (en) 2014-02-19
US9693492B2 (en) 2017-06-27
WO2012140934A1 (ja) 2012-10-18
CN103460377A (zh) 2013-12-18
EP2698819B1 (en) 2019-08-14
JP5693710B2 (ja) 2015-04-01
EP2698819A4 (en) 2014-10-01
US20140085858A1 (en) 2014-03-27
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