JP2010263192A - 回路パターンの浮き上がり現象を抑制するパッケージオンパッケージ及びその製造方法 - Google Patents
回路パターンの浮き上がり現象を抑制するパッケージオンパッケージ及びその製造方法 Download PDFInfo
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- JP2010263192A JP2010263192A JP2010081168A JP2010081168A JP2010263192A JP 2010263192 A JP2010263192 A JP 2010263192A JP 2010081168 A JP2010081168 A JP 2010081168A JP 2010081168 A JP2010081168 A JP 2010081168A JP 2010263192 A JP2010263192 A JP 2010263192A
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- package
- copper post
- semiconductor package
- sealing material
- lower semiconductor
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- 230000007547 defect Effects 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 224
- 229910052802 copper Inorganic materials 0.000 claims abstract description 102
- 239000010949 copper Substances 0.000 claims abstract description 102
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 100
- 229910000679 solder Inorganic materials 0.000 claims abstract description 74
- 239000003566 sealing material Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 31
- 230000008707 rearrangement Effects 0.000 claims description 22
- 238000007789 sealing Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 3
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- 150000001879 copper Chemical class 0.000 claims description 2
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Abstract
【解決手段】本発明のパッケージオンパッケージは、内部に複数の半導体チップが積層された下部半導体パッケージと、下部半導体パッケージの上部面の封止材の一部を除去して設けられ、封止材より高さが低い銅ポスト形態の連結部と、下部半導体パッケージの連結部にソルダーボールを通じてファンイン構造で連結される上部半導体パッケージと、を備える。これにより、下部半導体パッケージの最上部の半導体チップの回路パターンの浮き上がり問題を解決でき、上/下部半導体パッケージ間のソルダー接合の信頼度を高め得る。
【選択図】図1
Description
本発明の他の目的は、半導体パッケージの高さを低くさせつつ、ソルダー接合信頼度を向上させて、回路パターンの浮き上がり欠陥を抑制できるPOPの製造方法を提供することにある。
本発明の望ましい実施形態によれば、前記下部半導体パッケージは、パッケージ製造用の基板と、前記基板上に積層された複数の半導体チップと、前記積層された最上部の半導体チップの表面に形成されたパッド再配置パターンと、前記パッド再配置パターンの連結端子上に形成された銅ポストと、前記半導体チップと前記基板とを連結するワイヤと、前記基板の上部、半導体チップ、ワイヤ及び銅ポストを密封する封止材と、前記基板の下部に付着されたソルダーボールと、を備えることが適している。
また、本発明の望ましい実施形態によれば、前記積層された複数の半導体チップは、第1及び第2傾斜を有するように階段型に前記基板上に積層されることが適し、前記下部半導体パッケージは、前記基板の他の領域に搭載されて前記基板とワイヤで連結される受動素子を更に備えることが適している。
望ましくは、前記連結部の銅ポストは、前記銅ポストの側面及び上部表面にソルダーがメッキされるか、又は上部表面にのみソルダーがメッキされることが適し、中間部分が空いている形態もある。
一方、前記封止材の一部が除去された形状は、前記銅ポストの一部のみが外部に現れるように除去されるか、又は前記銅ポスト全体が外部に現れるように除去されたものでもある。
前記上部半導体パッケージのソルダーボールの一部は、前記下部半導体パッケージの封止材の高さより低い高さで前記連結部の銅ポストと連結されることが適し、前記回路パターンの浮き上がり現象を抑制するPOPは、前記下部半導体パッケージと前記上部半導体パッケージとの間を充填するアンダーフィルを更に備え得る。
本発明の望ましい実施形態によれば、前記下部半導体パッケージは、半導体パッケージ用の基板を準備する工程と、前記基板上に複数の半導体チップを第1及び第2傾斜を有するように階段型に積層する工程と、最上部にパッド再配置パターン及び銅ポストが形成された半導体チップを積層する工程と、前記半導体チップと前記基板とをワイヤで連結する工程と、前記基板の上部、半導体チップ、ワイヤを封止材で密封する工程と、前記基板の下部にソルダーボールを付着する工程と、を含んで設けられることが適している。
望ましくは、前記下部半導体パッケージの封止材の一部を除去して前記銅ポストを露出させる方法は、前記銅ポストが完全に露出されるように除去するか、又は前記銅ポストが一部露出されるように除去することが適している。
一方、前記最上部にパッド再配置パターン及び銅ポストが形成された半導体チップは、前記銅ポストの表面にソルダーがメッキされたものを使用することが適し、前記銅ポストにソルダーがメッキされた形態は、前記銅ポストの側面と上部面とにソルダーが同時にメッキされた形態であるか、又は前記銅ポストの上部面にのみソルダーがメッキされた形態であることが望ましい。
また、本発明の望ましい実施形態によれば、前記下部半導体パッケージの封止材の一部を除去して銅ポストを露出させる方法は、レーザエッチングを利用して前記銅ポストを露出させるか、又はマスクを使用したドライエッチング或いはウェットエッチングを利用して前記銅ポストを露出させるか、又は銅ポストの形成後に離型フィルムを銅ポストに付着する工程と、離型フィルムが付着された下部半導体パッケージを封止材で密封する工程と、前記封止材の密封が完了した後に前記離型フィルムを除去する工程と、を通じて前記銅ポストを露出させ得る。
本発明の望ましい実施形態によれば、前記上部半導体パッケージのソルダーボールが前記銅ポストに接合される位置は、前記下部半導体パッケージの封止材の高さより低いことが適している。
第二に、上部半導体パッケージのソルダーボールが下部半導体パッケージの封止材内に埋め込まれる構造であるため、POPの全体高さを低められ、上部半導体パッケージのソルダーボールの高さが低くなるだけ、ソルダーボール間のピッチを狭めることが可能であり、これにより、POPの設計工程でソルダーボールの配置を更に容易にできる。
第三に、上部半導体パッケージのソルダーボールが下部半導体パッケージの銅ポストと連結されて封止材内に埋め込まれる構造であるため、温度サイクル信頼度検査で下部半導体パッケージの封止材が温度変化によるストレスを吸収するバッファ層の役割を行える。これにより、下部半導体パッケージの最上部の半導体チップで温度変化によるストレスによって回路パターンの浮き上がり欠陥が発生することを防止して、POPでソルダー接合信頼度(SJR:Solder Joint Reliability)を改善できる。
第四に、上部及び下部半導体パッケージに対する電気的検査を完了した後、良品である二つの個別半導体パッケージを連結するため、上部及び下部半導体パッケージを上下に連結した後、個別上部及び下部半導体パッケージで電気的不良が発生する問題を防止できる。
110、310 基板
111 ボンドパッド
112 ボンドフィンガー
113 パッド再配置パターンの連結端子
114、314 ソルダーボールパッド
116 半導体チップ
118 パッド再配置パターン
120 銅ポスト
122A、122B ソルダー
130 第1ワイヤ
132 第2ワイヤ
134 第3ワイヤ
140 受動素子
150、350 封止材
160、360 ソルダーボール
170 離型フィルム
200 連結部
300 上部半導体パッケージ
1000 パッケージオンパッケージ(POP)
Claims (20)
- 回路パターンの浮き上がり現象を抑制するパッケージオンパッケージであって、
内部に複数の半導体チップが積層された下部半導体パッケージと、
前記下部半導体パッケージの上部面の封止材の一部を除去して設けられ、該封止材より高さが低い銅ポスト形態の連結部と、
前記下部半導体パッケージの連結部にソルダーボールを通じてファンイン構造で連結される上部半導体パッケージと、を備えることを特徴とするパッケージオンパッケージ。 - 前記下部半導体パッケージは、
パッケージ製造用の基板と、
前記基板上に積層された複数の半導体チップと、
前記積層された最上部の半導体チップの表面に形成されたパッド再配置パターンと、
前記パッド再配置パターンの連結端子上に形成された銅ポストと、
前記半導体チップと前記基板とを連結するワイヤと、
前記基板の上部、半導体チップ、銅ポストを密封する封止材と、
前記基板の下部に付着されたソルダーボールと、を備えることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記積層された複数の半導体チップは、
第1及び第2傾斜を有するように階段型に前記基板上に積層されることを特徴とする請求項2に記載のパッケージオンパッケージ。 - 前記下部半導体パッケージは、
前記基板の他の領域に搭載されて前記基板とワイヤで連結される受動素子を更に備えることを特徴とする請求項2に記載のパッケージオンパッケージ。 - 前記連結部の銅ポストは、
前記銅ポストの側面及び上部表面にソルダーがメッキされるか、又は上部表面にのみソルダーがメッキされることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記連結部の銅ポストは、
中間部分が空いている形態であることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記封止材の一部が除去された形状は、
前記銅ポストの一部のみが外部に現れるように除去されることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記封止材の一部が除去された形状は、
前記銅ポストの全体が外部に現れるように除去されることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記上部半導体パッケージのソルダーボールの一部は、
前記下部半導体パッケージの封止材の高さより低い高さで前記連結部の銅ポストと連結されることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 前記パッケージオンパッケージは、
前記下部半導体パッケージと前記上部半導体パッケージとの間を充填するアンダーフィルを更に備えることを特徴とする請求項1に記載のパッケージオンパッケージ。 - 回路パターンの浮き上がり現象を抑制するパッケージオンパッケージの製造方法であって、
複数の半導体チップが積層された構造であり、最上部の半導体チップにパッド再配置パターンが形成され、該パッド再配置パターンの連結端子に銅ポストが形成された下部半導体パッケージを準備する工程と、
前記下部半導体パッケージの封止材の一部を除去し、前記銅ポストを露出させて連結部を形成する工程と、
複数の半導体チップが積層された上部半導体パッケージのソルダーボールを前記下部半導体パッケージの連結部の銅ポストにファンイン方式で接合させる工程と、を有することを特徴とするパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージは、
半導体パッケージ用の基板を準備する工程と、
前記基板上に複数の半導体チップを第1及び第2傾斜を有するように階段型に積層する工程と、
最上部にパッド再配置パターンと銅ポストとが形成された半導体チップを積層する工程と、
前記半導体チップと前記基板とをワイヤで連結する工程と、
前記基板の上部、半導体チップ、ワイヤを封止材で密封する工程と、
前記基板下部にソルダーボールを付着する工程と、を含んで設けられることを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージの封止材の一部を除去して前記銅ポストを露出させる方法は、
前記銅ポストが完全に露出されるように除去することを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージの封止材の一部を除去して前記銅ポストを露出させる方法は、
前記銅ポストが一部露出されるように除去することを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記最上部にパッド再配置パターンと銅ポストとが形成された半導体チップは、
前記銅ポストの表面にソルダーがメッキされたものを使用することを特徴とする請求項12に記載のパッケージオンパッケージの製造方法。 - 前記銅ポストにソルダーがメッキされた形態は、
前記銅ポストの側面と上部面とにソルダーが同時にメッキされた形態であるか、又は前記銅ポストの上部面にのみソルダーがメッキされた形態であることを特徴とする請求項15に記載のパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージの封止材の一部を除去して銅ポストを露出させる方法は、
レーザエッチングを利用して前記銅ポストを露出させることを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージの封止材の一部を除去して銅ポストを露出させる方法は、
マスクを使用したドライエッチング或いはウェットエッチングを利用して前記銅ポストを露出させることを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記下部半導体パッケージの封止材の一部を除去して銅ポストを露出させる方法は、
銅ポストの形成後に離型フィルムを銅ポストに付着する工程と、
離型フィルムが付着された下部半導体パッケージを封止材で密封する工程と、
前記封止材の密封が完了した後に前記離型フィルムを除去する工程と、を通じて前記銅ポストを露出させることを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。 - 前記上部半導体パッケージのソルダーボールが前記銅ポストに接合される位置は、前記下部半導体パッケージの封止材の高さより低いことを特徴とする請求項11に記載のパッケージオンパッケージの製造方法。
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