TW201044548A - Package on package to prevent circuit pattern lift defect and method of fabricating the same - Google Patents

Package on package to prevent circuit pattern lift defect and method of fabricating the same Download PDF

Info

Publication number
TW201044548A
TW201044548A TW099110562A TW99110562A TW201044548A TW 201044548 A TW201044548 A TW 201044548A TW 099110562 A TW099110562 A TW 099110562A TW 99110562 A TW99110562 A TW 99110562A TW 201044548 A TW201044548 A TW 201044548A
Authority
TW
Taiwan
Prior art keywords
package
semiconductor
conductive
semiconductor package
substrate
Prior art date
Application number
TW099110562A
Other languages
English (en)
Inventor
Kyung-Man Kim
In-Ku Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW201044548A publication Critical patent/TW201044548A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

201044548 34ϋ33ριί' 六、發明說明： 【相關申請案】 本申請案主張2009年5月8日於韓國智慧財產局提 出申清之韓國專利申請案第1〇_2〇〇9_〇〇4〇29〇號的權益， 此案之全文併入本案供參考。 【發明所屬之技術領域】 本發明是有關於一種先進型半導體封裝及其製造方 法，且特別是有關於—種層疊封裝(package on package ， POP)及製造層疊封裝的方法，其中層疊封裝中的兩個半導 體封裝彼此垂直連接。 【先前技術】 隨著可攜式電子裝置的尺寸減小，半導體封裝的尺 寸、厚度以及重量也隨之減小。在習知的半導體封裝中， 會將具有單—魏的半導體難安肢可狱電子裝置的 主印刷電路板(PCB)上。近年來，也可以將具有兩種 種功能的先進型半㈣縣絲於主印刷電路板上。 諸如系統封裝(SIP)、多晶片封裝(Mcp)以及層疊封農 (POT)之整合财導體難是歧型半導體賊的血型實 例。在整合料導體聽中’在對兩辦導體封裝騎完 整組合及對每—半導體封裝層疊封裝進行電性測試 (electrical test)後，層疊封裝將兩個半導體封舻人而為一 由於在對每—半導騎裝的雜雜撕職彳I，半^ 封裝是以無缺陷(defect-free)狀態進行組合，因此在半 封裝組合成層疊封裝狀祕’可餅低電⑽陷的產生。- 201044548 34U^3pir 此外，具有不同功能的半導體封裝 封裝。 、、口 口成早一半導體 【發明内容】 本發明為提供-種料封裝(PQP)，❹ 較小高度之半導體封裝且在銲接接 有 度，如此-來可以避免電路圖案隆起缺陷有較佳的可靠 ο ❹ 將在下文_敘述本發明的其他方面及 敘述’可以清楚本發明之其他未描述的部分， 經由施行本發明而習得這些其他部分。 -者疋了以 本發明的特徵及/或用途可以層疊 部半導體封裝以及連接部，其 «=疊的半導體晶片’以及連接部包括高 的銅柱。位於下部半導體封裝的上表面上的部分包 =’上部半導體封裝經由第-二 式連接至下部半導體封裝的連接部。 墓骑Γ科導體封裝可包括基板、堆疊於基板上的多個半 =體曰曰片、銲墊重配置圖案、銅柱、導線、包覆構件以及 。銲塾重配置圖案形成於堆疊之半導體晶片的頂 導體晶片的表面上。銅柱形成於銲塾重配置圖案 t °導線連接多個半導體晶片中的每一者與基板。包覆 霉件包覆基板的上表面、多個半導體晶片以及銅柱 銲球附著於基板的下表面。 〜 5 201044548 34033pif 〃多個半導體晶片可在第-方向上堆疊於基板上， 母半導體曰曰片及與其相鄰的母一半導體晶片在第-方θ 上偏置(offset)，其中第二方向垂直於第一方向。下部半導 體封裝可更包括減裝置，保魏置絲於基板上並夢由 導線與基板連接。 3 銲料可鍍在連接部的銅柱之側表面與上表面中至少 一者上。連接部的銅柱的中心部分可以是中空的。 移除部分包覆構件可僅暴露出銅柱的一部分或全部。 上部半導體封裝的部分鋅球可在一高度處連接至連 ，部的銅柱，所述高度低於下部半導體封裝的包覆構件的 同度。層g封裝可更包括底膠，底膠填滿下部半導體封裝 與上部半導體封裝之間的空間。 本發明的特徵及/或用途亦可以層疊封裝的製造方法 來實現以避免電路圖案隆起缺陷。所述方法包括：準備具 ，堆疊之多個半導體晶片的下部半導體封裝；於頂半導體 晶片上形成銲墊重配置圖案；於銲墊重配置圖案的連接端 上形成銅柱；藉由移除位於下部半導體封裝上的部分包覆 構件以暴露銅柱並形成連接部；以及將包括堆疊之多個半 導體晶片的上部半導體封裝的第一銲球以扇入結構的形式 輕接至下部半導體封裝的連接部的銅柱。 下部半導體封裝可由以下方法製造。所述方法包括： 準傷用於半導體封裝的基板；於基板上堆疊多個半導體晶 片且使半導體晶片彼此偏置；於堆疊之多個半導體晶片的 201044548 34033pit 最上方半導體晶片上堆疊最上方半導體晶片㈣㈣⑽ sem1Conductor chip) ’且最上方半導體晶片具有銲墊重配置 圖案與導電柱；使用導線連接半導體晶片與基板；以包覆 構件包覆基板的上部分、半導體晶片以及導線；以及將第 一銲球附著至基板的下部分。 ❾
G =由移除位於下料導贿裝上的部分包覆構件 柱的步驟中，可移除包覆構件以完全地或部分地 部上ίΪΪΪ重配置圖案與銅柱形成於半導體晶片的頂 邛上的步驟中，銲料可鍍在銅柱的表面上。 鐘在雖⑽表面舆上表面上或者是僅 以最除位於下部半導體封裳上的部分包覆構件 二央t驟中’可藉由雷射蝕刻或使用罩幕的乾式 ===銅柱。移除位於下部半導體封裝上之部 片附著至銅柱上^由銅柱後，將脫膜 構件進封裝;以及在使用包覆 …復4兀成後，移除脫臈片以暴露銅柱。 部半====辦崎可低於下 導體導㈣料實現。半 牛^體曰曰片堆疊、覆蓋半導體晶片堆 7 201044548 34033pif 晶片堆叠之上表面。導電::=二面=半導雜 且在凹槽處突出於包覆層。+¥體曰曰片堆疊電性連接 個半導體晶片堆#可包括在彼此上方堆叠的多 半導體晶片堆疊可包括至少一重 疊於半導體晶片堆疊之最上 上層堆 及導電引線可電性連接至重配置層。曰片的上表面上，以 裝堆導體縣，上部半導體封 υ堆4上且電性連接至導電引線。 導電引線的高度可低於包覆声 電引線的高度可高於包覆層的H的f表面。可選地，導 形、雜可以是+字形、五邊形、圓 導電引線可具有中空的中心。 導電弓丨線的表面可塗佈有銲料層。 導體引線可包括第一端與第二端，其中第—端接觸半 半導體=上表面’以及第二端與第一端相對且朝上表面 的基部，2相反方向延伸’以及包覆層可接觸導電引線 可選地=中導電引線的基部與導電引線的第—端相鄰。 进也’包覆層可不接觸導電引線。 201044548 至少一半導體晶片堆疊可包括基板、堆疊之多個半導 體晶片以及至少一導線。每一半導體晶片及與其相鄰的每 一半導體晶片偏置，堆疊之半導體晶片的最下方半導體晶 片安裝於基板上，以及導線連接每一半導體晶片及與其相 鄰的每一半導體晶片。 包覆層圍繞多個半導體晶片中的每一者及至少一導 線。 ❹ ❹ 本發明的特徵及/或用途亦可以半導體封裝的形成方 法來實現。所述方法包括：形成導電引線，使導電引線由 半導體晶片堆疊的上表面突出；形成包覆層，以覆蓋半導 體晶片堆登的上表面；以及移除圍繞引線的包覆層，以於 包覆層中形成凹槽。 所述方法可更包括於導電引線的表面上形成銲料層。 所述方法可更包括將上部半導體封裝安裝於半導體 晶上，上部半導體封裝具有對應於包覆層之凹槽的 至少-銲球’銲球電性連接至導電引線。 2明的特徵及/或用途亦可以計算裝置來實現。計算 L❹里單元與功能單元。處理單元包括處理器與邏 :功能單元包括至少—記憶體晶片。計算裝 ==封裳。半導體封裝可包括至少一半導體晶片堆 J疊S苡及i線。包覆層覆蓋半導體晶片 包覆声的表面上具有至少-凹槽，其中 曰的上表面賴於半導體晶片堆疊之上表面。導電引 9 201044548 34033pif 線電〖生連接至半導體晶片堆疊且在凹槽處突出於包覆層。 處理器、邏輯單元以及記憶體晶片中的至少一者為至少〜 半導體晶片堆疊中的半導體晶片。 ^為讓本發明的這些及/或其他觀點及功效能更明顯易 懂’下文特舉實施例，並配合所關式作詳細說明如下。 【實施方式】 卜接下來將參看附圖更全面地描述本發明的示範性實 施=但本發明可舰爲多料同的形式且*應被認爲限 於文所述的實施例’且在不脫離本發明之精神和範圍 内’當可作些許之更動與潤飾。換言之，針對特定結構或 功能所進行的描述贱為了 _本發㈣示紐實施例。 現將詳述本發明之實施例，且這些實例繪示於圖式 中，其中類似的元件符號表示類似的元件。將在下文中以 參照圖式的方式來描述本發明之實施例。 圖1為本發明之示範性實施例的層疊封裝〇 〇〇〇 ，構的剖面示意圖，其中層疊封裝能避免電路圖案隆起缺 層疊封裝1000包括下部半導體封裝1〇〇與導電引線 120’下部半導體封们⑻具有堆疊的多個半導體晶片 116,藉由移除下料導酸裝⑽的上表面上的部分包覆 構件150可由包覆構件或包覆層15G暴露出導電引線 120。舉例來說，導電引線12〇可為銅柱⑽。可選地，導 電弓ί線120可為金柱、銀柱、錫柱、銅、金、銀以及錫中 任一者的合金或由其他合適的導電材料所製成的柱。導電 引線120的南度可低於包覆構件bo的高度。上部半導體 201044548 OHUJJpii 封裝300可經由銲球36〇以扇入結構的形式連接至下部 導體封裝100的導電引、線12〇。下部半導體封襄削盘上 =半導體縣3〇()之__3可被諸如環氧概等底 填滿。 _ 避免電路®祕起缺陷騎㈣裝職可應用於 入結構’以連接上部半導體封裝與τ部半導體封裝 100。因此，可以避免因上部半導體封裝3〇〇與下部半導體 ❹封裝100的龜曲缺陷(warping defects)所造成的上部半導 封裝300與下部半導體封裝1〇〇之間的連接缺陷。 扇入結構為-種結構，其中上部半導體封裳· 部半導體封裝100之_連接不是在下部半導體封裝⑽ 的上表面，而是由上表面向内且朝向半導體晶片丨16所在 處的中央部分。扇出結構則是指上部半導體封裝3 〇 〇與 部半導體封裝100之間的連接位於下部半導體封裝丨⑽、 邊緣的結構。當上部半導體封裝300與下部半導體封裝100 縣板發生些微的㈣缺陷時，上料導體封裝的鮮 ϋ 360可連接至下部半導體封裝100的基才反，也就是說，可 能會產生嚴重的連接缺陷。本示範性實施例之具有扇入結 構的層疊封裝1000可避免上述連接缺陷。以羽νσ 在本示範性實施例之層疊封裝1〇〇〇中，銲墊重配 圖案118可形成於下部半導體封裝100的頂半導體晶片上 及導電引線上，或銅柱120可形成於銲墊重配置圖^ 118 的連接端處。藉由將上部半導體封裝300的銲球36〇'下 至下部半導體封裝100的包覆構件150的上表面下，上部 11 201044548 34033pif 半導體封裝300的鲜球可連接至導電引線i2〇。 體封^體的總高度’使得半導 _、，二 更卜，可以縮減銲球剔之間的 ^以^減半導體封裝的銲球細的高度。基於這此 =點’在設計層疊封裝画時，可以更隨意地配置鲜球 多種in導體封裝後’大部分的半導體封裝必須經過 試’崎查半導體縣的功能在嚴苛的環境 試，以檢查半_娜、:# *度賴可以是溫度測 产例η ^體封裝在〉皿度變化下的運作狀態。根據溫 二:置裝1〇00被置於·25。。的溫度下10分鐘且 以产杳的高溫下10分鐘，以及重複進行測試 一:=導體封裝的可靠度。在·25%與⑵。c之間進行 期iί—個週期。在重複進行測試達_個週 去欢—層宜封裝1000的電性及/或物理狀態。 loo ai, , +日曰片疋直接連接而無需使用導電引線120 因此带360與半導體晶片的熱膨脹係數(CTE)不同， 起或=於:二導體晶片上的電路圖案(未繪示)可能會隆 中，電路可能會產生漏電流。在較嚴重的狀況 中電路可能會斷接而產生嚴重缺陷。 上部ΐί體電引線12G的作用為緩衝，其能夠吸收 頂半導f s ^裝的銲球與下部半導體封裝100的 體曰曰片之間的_脹係數差異，因此層疊封裝酬 12 201044548 ^4U3ipit 會因為熱膨脹係數的差異而分配壓力。此外，由於上部半 導體封裝300的銲球360降至下部半導體封裝1〇〇的包覆 構件150的上表面下方，因此包覆構件15〇可吸收因熱膨 脹係數差異所造成的熱應力，以提升層疊封裝結構的銲點 可靠度(SJR)。 Ο Ο 上部半導體封裝300與下部半導體封裝1〇〇可被間隙 Β分離，其中銲球或連接器36〇定義間隙Β。與下部半導 體封裝100相似，上部半導體封裝3〇〇可包括包覆層或包 覆構=350以環繞上部半導體封裝的半導體晶片及導線， ^中這些構件的組態與下部半導體封裝削中的構件的組 態相似。下部半導體封裝亦可包括連接器或銲球⑽，伟 層疊封裝連接至另一電子裝置(未繪示）。 圖2Α與圖2Β為本發明之示範性實施例的下部半 封裝中堆疊之半導體晶片的剖面示意圖。請參照圖卜 t m2B，提供基板110且基板u〇可以是印刷‘ 板。於基板110的上表面上提供可裝置半導體晶片！ 晶片附著部分。可沿著晶#崎部分的邊緣形成接合於 112。此外，於基板110的下表面上提供銲球墊⑴。曰 最下方半導體晶片U6d可安裝於基板11〇的 著部分上。其他半導體晶片116可在第一方向丫上安^ 最下方半導體晶片116上以及可在第二方向χ1、χ最 下方半導體晶片偏置，其中第二方向χ1、χ2垂直於第二^ 向。如圖2Β所示’下半導體晶片肠可在第一 上與相鄰的半導體晶片丨16a偏置以形成階梯狀，以及°上^ 13 201044548 34033pif 導體晶片116b可在與第一方向y相對的第二方向^上與 相鄰的半導體晶片116b偏置。因此，下半導體晶片U6'a 彼此偏置以在大體上在介於方向xl與方向y之間的方向上 形成階梯狀，以及上半導體晶片116b可彼此偏置以大體上 在介於方向X2與方向y之間的方向上形成階梯狀。 半導體晶片堆疊可包括中央半導體晶片U6c，以及在 中央半導體晶片116c下的半導體晶片可為下半導體晶片 116a’以及在中央半導體晶片U6e上的半導體晶片可為上 半導體晶片116b。由於中央半導體晶片n6e是位於下 導體晶片116a與上半導體晶片116b之間，因此其不需要 位於堆疊之y方向的中心點處。舉例來說，下半導體晶片 116a可包括二個半導體晶片U6a，以及上半導體晶片⑽ 僅包括一個半導體晶片l16b。 最上方半導體晶片116e可包括銲墊重配置圖案⑴， 重Γ置圖案118可形成於或安裝於最上方半導體晶 、e 導電引線120可形成於銲塾重配置圖案118 =連接端上。賴裝置⑽亦可安裝於基板⑽上。舉例 來說’電阻器、電容器以及電感器可絲於基板ιι〇上， 2堆疊之半導體116中的—者或多者可與保 連接。 體晶片⑽可經由第一導線130連接至基板 、車垃5耸：曰112。上半導體晶片⑽可經由第二導線132 連接至基板110的接合指112。保護農置14〇可經由第三 導線134連接至基板的接合指。 14 201044548 34033pit 二===== U6内或卜成最上方半導體晶片 最上方半導體;片、;上或-層中，其中此層與 圖案118_的最上表面直接連接。銲墊重配置 Ο Ο ，上的銲塾出電性連接至連導： 可形成於連接端113上。 導电引線120 半導體晶片116上麟塾U1可沿著 的邊緣而軸為峨如圖3㈣），在轉 的中央處形成為兩列(如圖5戶Ut 晶片116 的導圖6B、圖6C與6D為本發明之示範性實施例 的V電引線120的不同形狀的平面示意圖。 導電引線12G可具有多種雜，諸如十字形(圖 五邊形（圖6B)、圓形（圖6C)或橢圓形（圖6D)。此外，如圖 7A與圖π所示，導電引線⑽可為中空的。舉例來說， 圖7A繪示中空的橢圓連接部12〇以及圖7B繪示中空的十 ^形連接部no。當導電引線120為中空的，因録球36〇 /、頂半導體晶片116之間的熱膨脹係數差異所導致的熱應 力可輕易地被吸收。 ^ 如圖14以及圖15A至圖15D所示，導電引線12〇可 塗佈有銲料層122a、122b。舉例來說’可以經由電鑛方式 15 201044548 34033pif 將銲料塗佈於導電引線120上。如圖14所示，銲料層122a 可位於導電引線120的側部與頂部上，或者是如圖Μ所 示，銲料層122b可僅位於導電引線12〇的上表面上。可選 地，如圖16所示，導電引線120也可以未經銲料層塗佈。 圖8為本發明之示範性實施例的下部半導體封裝的剖 面示意圖，其中已完成模製製程。基板11〇的上表面、^ 導體晶片116、導線130、132、134、銲塾重配置圖案118 以及導電引線120可完整地被包覆構件15G包覆。舉例來 說’包覆層或包覆構件15〇可為環氧樹脂模封材料㈣叫 m〇ldC〇mpound，EMC)。包覆構件15〇被模製成具有足以 完整地覆蓋導電引線12〇的厚度。 =為本制之錢性實_的下部半導贿裝的剖 面不思圖，其中藉由钕刻製程形成連接部 製程中’使用雷射移除部分包覆構件 ，暴路導電引線i2G的凹槽。此外，可藉由乾式鞋刻或渴 部分包覆構件150以形成暴露導電购的 一f在進行姓刻製程或進行包覆層150的移除製程之 别，導電引線12G未被銲料塗佈，則可以在 接 j ’再將銲料塗佈至導電弓丨線上。㈣可導1 引線120的上表面上或導電引線12〇的上表 導- 至圖1GC為本發明之示範性實施_下 體封衣的剖面示意圖，其中以使 ^ ，如…示，下二：裝來進=: 16 201044548 34033pit :5鬥\包1f模製製程之前’導電引線12Q可以被脫膜片 請圍繞。接著，使用包覆構件150包覆基板 二=:所示，脫膜片170的上表面會暴露於包覆構 然後，如圖loc所示，⑽模製之後， 移除脫糾Π0以形成暴露導電引線12G的連接部·。 圖11為本發明之示範性實施例的上 剖面示意圖’其中上部半導體封裂安裝於下; Ο Ο 上，且下部轉體封裝具有形成於其中之連接部ζ0。上 部半導體縣安裝於τ部半物封裝丨町，其中下 部半導體封裝100中形成有連接部 部 _⑻安襄於下部半導體封裝1〇〇上， =300的鲜球嵌入至連接部細巾，其中連接部2〇〇 下部半導體封裝⑽的上表面上，如此—來可形成 j扇人結構的層疊封裝咖。當對連接部Α進行回流製 f時’會溶化半導體封裝300的銲球_朋而轉電引 接。將參照圖12至圖14來詳細其結構。在連接 ^半導體縣300與下部轉體封裝i⑽之後，可使用 ^樹脂來進行填滿上料導體封裝與下部半導體封 裝100之間的空間B的製程。 圖12至圖η為本發明之示範性實施例的上部半導體 =裝=球連接至下部半導體封料連接部的剖面示意 曰雜照圖η，上部半導體封们⑻的基板⑽具有諸 t球墊的電性連接塾314。鮮球綱可形成於墊314上 且其位置職於下部轉體塊⑽的連接部·。可形 17 201044548 34033pif 成連接部200，以完全地暴露導 是同時鍍右道& ▼电W琛120。紅枓層122a 3=導+電引線120的上表面與側表面上。因此，當 ^+ ¥體封们⑻的銲球36g在 : 在使用•射以散佈在導電引線120周圍。 射蚀刻包覆構件15。時，鮮料層1-亦可編 表面13 ’焊料122b可僅錢在導電引線120的上 € 露出部分導電弓丨線120。換言之，若導暴 度hi，那麼圚达道雷2丨$ 電引線120具有向 :r:ri2_ 二二=° 差：;=:=合之材料之間的熱膨_ 12。1 = ;2=接部2〇°以部分地暴露導電引線 導W憎導^ 不具有任何銲料層。上部半 泠體封裝300的銲球360可在 十曰上科 地連接至導㈣線m。由於包雜化，以直接 19Λ n . 、L覆構件〗5〇圍繞導雷3丨么舍 及在于球360，因此在溫度週期測 、、、 及與其結合之材料之間的熱膨脹係冓件15〇 可被適當地吸收。 ”斤以成的熱應力 導電引線120可被組態成任何合適 圖Η所示，導電引線12〇的高度可低 1;、尺寸。如 換5之包覆層150與導電㈣〇之間的J差 18 201044548 34033pif 可為距離dl，其中dl為大於G的正數。因此，在以回流 製程溶化銲球之前，銲球360延伸至包覆層150的表面下 方一距離dl，以接觸導電引線。 &圖15A至圖15D繪示導電引線12〇與包覆層15〇的 組悲。在圖15A中，導電引線120安裝於重配置層118 上，以及包覆層15〇形成為具有距離d2，其中距離幻 包覆層150與導電引線12〇之間的距離。在圖15八中，距 〇 離d2為正數，使得導電引線120不會接觸包覆層15〇。 义另一方面，圖15B繪示接觸包覆層的導電引綠12〇。 如則文針對圖13所進行的敘述，接觸導電引線12〇 重配置層150可具有高度h2,以及導電引線120可具^ 度M。由於僅部分導電引線120被包覆層150園緣，^ 為大於h2的正數。包覆層150以及形成於包覆層15〇 1 連接部200可與導電引、線120之間具有預定的關係的 來說’包，層150可具有高度h3,其中高度h3為導:例 線120的高度hi的兩倍。可選地’連接部2〇〇的含弓丨 可為導電引線12G之暴露部分的高度(以高度Μ 的兩倍。 表禾) 如圖15C所示，當銲料層122a塗佈於導電弓丨 的側部時’銲料層122a與包覆層15〇可分離且兩者線 有距離d3。此外，若導電引線12〇具有寬度私，^間鳥 122a可具有寬度d5,其中寬度必實質上小於導電飞科層 的寬度d4。舉例來說，銲料層122a可具有寬度如綠 d5為導電引線120的寬度d4的1/4或小於導電 見度 丨緣120 19 201044548 34033pif 的寬度d4。 、在圖15D中，銲料層122a與包覆層150之間的距離 d3為0 ’換言之，包覆層15〇接觸部分銲料層η。。如上 述包後層150可僅圍繞部分銲料層ma，以及圍繞焊料 層122a的包覆層15〇部分可具有高度h2。 圖16A與圖16B繪示將銲球360熔化至導電引線12〇 上的製程。如圖16A所示，在進行熔化之前，上部半導體 封裝300的銲球36㈣最底部分會接觸導電引線12〇的上 表面，其中銲球360的最底部分位於包覆層150之上表面 下且與包覆層150之上表面之間具有雜dl。上部半導體 封裝之基板310的底表面與下部半導體封裝之包覆層15〇 的上表面分離且兩者之間具有距離d6。銲球36〇可形成於 連接墊314上，其中連接墊314形成於基板31〇中。導電 引線120可形成於重配置層U8上。 於熔化銲球360時，上部半導體封裝之基板31〇 表面與下料導酸裝之包覆層⑼的上表面分離且兩者 之間具有小於距離d6的距離d7。此外，可熔化構成銲球 360的銲料以完整地圍繞導電引線12〇。因此，堆疊之上部 半導體封裝300與下部半導體封裝100之體積可=較小= 緊岔且可具有穩固的電性連接。此外，由於銲球是形 成於連接部200中，因此不太可能會散佈於包覆層15〇^ 上基板310的表面上’故可將層疊封裝1〇〇〇設計為使銲球 360的位置彼此接近。 圖17A至圖17D繪示連接上部半導體封裝3〇〇與下 20 201044548 34033pif 邛半^體封裝100的連接部200。圖17A繪示導電引線120 具有形成於其外表面上的銲料層122a。圖17B繪示導電引 線120具有僅位於其最上表面上的銲料層122b。導電引線 形成於重配置層118上，以及包覆層i5Q形成為覆蓋重配 置層118。鲜球360形成為上部半導體封裝300之基板310 的連接墊314上。 銲球360接觸銲料層122a之上表面且位於包覆層15〇 之上^面下方一距離刖處。如前文針對圖14與圖16A所 述’導電引線12G的最上表面與包覆層的最上表面之間的 3為距離di。由於圖17A與圖17B的導電引線12〇於 ，、取上表面上更包括另一銲料層122a、122b，距離dl大 於距離d8。換έ之，在進行炼化之前，圖17八與圖up ft球^可下降至包覆層15G的上表面下方的一距離狀 ί 小於定義為導電引線120的上表面至包覆 曰 的上表面之間的距離（即距離di)。
可《又。十電引線12〇、連接部2〇〇以及銲料層122及、 得^離^^之間具有想要的關係。舉例來 m电引、^ 12G可具有高度M以及包覆層150可具有高 2 ，使得熔化銲球360之前，銲球360的1/4位於包覆 層150的最上表面下方。 、 如®I 17C與圖17D所示’姐化銲球3⑼之後，亦可 ^化銲料層122a、122b且使銲料層心 地、化學㈣及/或電轉接至銲球細， 與導電引㈣之_電性連接。此外，峰 21 201044548 34033pif 熔化的銲料會至少填滿部分連接部2〇〇，因 下表面會移動成更靠近包覆層15〇的上 j 0的 板310盘包覆声15〇的ϊε拙:π 又’使知分離基 极取、包覆層150的距離d7小於在炫化鲜球細 以勿離基板310與包覆層15〇的距離舶。 且有::二與:/8B繪示連接部200，其中導電引線120 ^大於包覆層15G之高度h3的高度Μ。在圖i8A中， ^Ϊ 基板310的連接塾314。在炫化銲球360 ^ ’㈣360的底部與包覆| 15〇的上表面之間呈有距 ^㈣。如圖_戶斤示，一旦熔化銲球360，上基板31〇 2動成更靠近下部半導體縣漏的包覆層15〇，以及 ，電引口線no會與連接墊314分離且兩者之間具有距離 。只要在炼化銲球36〇之後，分離基板3ι〇與包覆層 150之間的距離d7能小於銲球36〇的高度，則距離犯可 為任何大於0的數值。 圖19繪示本發明之實施例的計算單元9〇〇，其可與半 ?體封裝結合。計算單元_可包減理單元91()與功能 單元920。處理單元91〇可包括處理器9丨2、邏輯單元gw 以憶單元916，記憶單元916例如是諸如快速記憶體。 功^元920例如是可包括邏輯單元922、記憶體似以 及介面926。介面926可包括諸如鍵盤或觸控螢幕等使用 者介面以及諸如有線或無線資料連接等電子介面。即使圖 19中所示的處理單元910的元件以及功能單元920的元件 ^分離的，但處理單元910與功能單元920也可以共用同 一 70件。舉例來說，邏輯單元914、922可以是處理單元 22 201044548
J4UJJpiI 910與功能單元920所使用的單—邏輯單元。 在計算單元_巾’任-半導體元件可包括本發明之 :實施例的層疊封裝麵。舉例來說，層疊封裝麵可 ^括至少-邏輯單元914、下部半導體封们⑻中的至少 己憶體晶片916以及上部半導體封裝3〇〇中的 個記憶體晶片924。邏輯箪元, i 夕 Ο ο 的記憶體9丨6可經由如上所述之半導體封裝觸 出戈上所述之導電引線120盥銲玻360 電性連接至上部半導體封们⑻的記憶體晶片92心 被===〇可包括處理器或可經由位於下基 ;: 的銲球160連接至處理請或邏輯單 二9Μ。處理H 912可與τ部半導 體封裝300的半導|#。日Η 11Α从入彳衣川υ興上口 μ牛導 片116之半導體梦晋的曰链来、^口，以根據組成半導體晶 料以及將資料“記憶體㈣處理_、岐賴讀取資 因上部與下部半導體封裝的= J接，因此可避免 半導體封裝的軸缺陷。曲㈣所產生之上部與下部 封裝:ί覆：Ϊ部:=埋在下部半導體 上部半導體封裝之銲球的:二裝H南度可以變小。當 間距此:此由:達f銲球Μ:效=減銲球之間的 封裝的包覆構件= 銲球是埋在下部半導體 下。卩半導體封裝的包覆構件可作 23 201044548 34033pif 為緩衝層，以吸_如在溫度職可靠度·巾因溫度變 ^匕所造成的應力。因此，可藉由避免產生因下部半導體封 裝之頂半導體晶片的溫度變化所導致的電路 陷，來改善層疊封裝的銲接接點可靠度。 ^ 、 再者，在對上部與下部半導體封裝進行電性 :立且為高質量產品Pr°dUCt)的半導體封裝 彼此連接。g]此’ ±部與下料導體魏•直連接且 此可避免上部與下部半導體難巾產生電性缺陷。 雖然本發明已以其實施例詳細地表示及描述，缺 2離本發明後附之申請專利朗之精 ς 瞭解到在其中可作各種形式及細節的改變。田了 【圖式簡單說明】 圖，Ξ 性實施例的層疊縣的剖面示意 圓，、中層4封裝能避免電路圖案隆起缺陷。 封裝ΓίΔ與圖2Β為本發明之不範性實施例的下部半導體 、的半導體晶片的堆4綠㈣面示意圖。 裝的頂圖例的下部半導體封 例的銅柱的二的平圖：6二:本發明之示範性實施 體封裝中的料導體晶片I騎銅柱形成於下部半導 圖7A輿圖7B為本發明之+ # u 形狀的平面示意圖，其中銅柱形二;他 頂半導體W上。 Ά於T科賴封裝中的 24 201044548 34033ρίί 圖8為本發明之示範性實施例的下部半 面示意圖，其中已完成模製製程。 叹的剖 圖9為本發明之示範性實施例的下部 面示意圖，其中藉祕刻製㈣成連接部。導體縣的剖 圖10Α至圖10C為本發明之示範性實施例的下 體封裂㈣意_，其巾以使舰則細 圖11為本發明之示範性實施例的上部半導體封 Ο ❹ = = =體封裝安裝於下部半導體狀 下°卩牛導體封裝具有形成於其中之連接部。 M L12至圖14為本發明之示紐實施_上部半導體 =的銲球連接至下部半導體封裝的連接部的剖面示ί 綠ΛΑ圖ΜΑ至圖15D 4本發明之示範性實施例的導電引 線的示意圖。 1 圖16A與圖16B為本發明之示範性實施例的接合 與導電弓丨線的示意圖。 圖17A至圖17D為本發明之示範性實施例的接合銲 球與導電引線的示意圖。 圖18A與® 18B為本發明之示紐實施綱導電引線 的示意圖。 圖19為本發明之示範性實施例的計算裝置的示意圖。 【主要元件符號說明】 100 :下部半導體封裝 110、310 :基板 25 201044548 34033pif 111 :銲墊 112 :接合指 113 :連接端 114 :銲球墊 116、116a、116b、116c、116d、116e :半導體晶片 118 :重配置圖案 120 .導電引線、銅柱 122a、122b :銲料層 130、132、134 :導線 140 :保護裝置 150、350 :包覆構件、包覆層 160、360 :銲球 170 :脫膜片 200、A :連接部 300 :上部半導體封裝 314 :墊 900 :計算單元 910 :處理單元 912 :處理器 914、922 :邏輯單元 916 :記憶單元、記憶體晶片、記憶體 920 :功能單元 924 :記憶體、記憶體晶片 926 :介面 26 201044548 34U33pit 1000 :層疊封裝 B :間隙、空間 hi、h2、h3、h4 :高度 dl、d2、d3、d4、d5、d6、d7、d8、dlO、dll :距離 xl、x2、y :方向
27

Claims (1)

  1. 201044548 34033pif 七、申請專利範圍： L層疊封裝，包括： Γίί導體封装，包括至少一半導體晶片； 導所述下部半導體封裳的上表面上. 导電柱，位於所述下部半導體封裝的上 ， ¥電柱的高度低於所述包覆層的上表面；^上’所迷 上部半導體封裝，經由第一鋒球以扇入 接至所述下部半導體封裝的所述導電柱。、。構的形式連 2.如申請專利範圍第1項所述之層最 述下部半導體縣包括： U情’其令所 基板； 多個半導體晶片，堆疊於所述基板上； 銲墊重配置圖案，位於堆疊之所述半導體晶片之最上 方半導體晶片的最上表面上，所述重配置圖案包括連接 端’以及所述導電柱位於所述連接端上； 導線，連接所述多個半導體晶片中的每一者與所述 基板； ~ 所述包覆構件，包覆所述基板的所述上表面、所述多 個半導體晶片以及部分所述導電柱；以及 第二銲球，附著於所述基板的下表面。 3.如申請專利範圍第2項所述之層疊封裝，其中： 所述多個半導體晶片在第一方向上堆疊， 多個下半導體晶片中的每一者及與其相鄰的每一下半 導體晶片在第二方向上偏置，其中所述第二方向垂直於所 28 201044548 » Ο ο 述第一方向，以及 導體片中的每-者及與其相鄰的每-上半 向相對。上偏置’所述第三方向與所述第二方 &申請專利範圍第2項所述之層疊封裝， 並错由導線與所述基板連接。 料丄ΐ申請專利範圍第1項所述之層疊封裝，1中铲 枓疋鑛在所述導紐之侧表面與上表面中至少—者1中杯 6. 如申請專利範圍第i項所述之 中 述導電柱的中心部分為中空的。 了展其中所 7. 如申請專利範圍第i項所述之層疊封裝，其 有部分所述導電柱位於所述包覆層外。 ” 8. 如申請專利範圍第1項所述之層疊封裝，其 個所述導電柱位於所述包覆層外。 x “ 正 9.如申睛專利範圍第1項所述之層疊封裝，其中戶 述上部半導體封裝的部分所述第一銲球在_高度處^接= 所述連接部的所述導電柱，所述高度低於所述半導^ 封裝的所述包覆構件的最上方表面。 1〇·如申請專利範圍第1項所述之層疊封裝，更包括 底膠，所述底膠填滿所述下部半導體封裝與所述上部半導 體封裝之間的空間。 n.〆種層疊封裝的製造方法，包括： 堆4多個半導體晶片，其中每一半導體晶片堆疊於另 29 201044548 34033pif 一半導體晶片的頂部上； 片中的頂半導體晶片上形成銲墊 於所述多個半導體晶 重配置圖案； 己置圖案的連接端上形成導電柱； ^^ 以覆蓋所述鮮塾重配置圖案的上表面； 接部;9以及于'部分所述包覆層以暴露所述導電柱並形成連 12. 方、> 專利範圍第U項所述之層疊封裝的製造 ，準備基板部半導體縣^町方絲造，包括： 痛+在向上將多個半導體晶片堆疊於所述基板上， ，二方向上偏置’其中所述第二“= 向； j 將最上方半導體晶片堆疊於堆疊之 片上’所述;上方半導體晶片具有形成於其ί表 墊重配置圖案與導電柱； 的逢干 使用導線將每—半導體晶片連接至所述基板； 以戶斤=覆層至少包覆所述基板的上表面、 方半導體晶片以及所述導線；以及 I·11 將第二銲球附著至所述基板的下表面。 30 ο G 201044548 方法專利範園第11項所述之層#封裝的製造 二整個述包覆層包括移除部分所述包覆層 方去141:料郷_ 11韻述之騎縣的製造 ίΐ杜 於所釘料導體賴上之部分所述包 覆構件，以部分地暴露所述導電柱。 方申請f利範圍第12項所述之層叠封裝的製造 方法/、t知料是鍍在所述導電柱之表面上。 \如申請專利範圍第15項所述之層叠 ::少:::述銲料是鍍在所述導電柱之側表面與上表面 17.如申請專利範圍第U項所述 •如甲δ月專利乾圍弟11項科汗+ a身 方t其中移除位於所述下部半導::3:= 覆構:t是藉由t用罩幕，乾式或濕絲刻來ί:逃包 方法，其中移除位於所述下部半^ 且封震的製造 覆廣包括： & W封裝上之部分所述包 im電柱後’將脫膜片附著至所述導電检上. 藉由使用所述包覆層來包覆所述下部半導n柱上， 中所述脫膜片附著至所述下部 ^魏，其 述=述包覆步驟完成之後，移除二：暴露所 31 201044548 34ϋ33ριί' 20. 如申，專利範圍第U項所述之層疊封装的 方法，其中辨接至所述導電柱的所述第_銲球延伸至^ 下部半導體封裝的所述包覆層的所述上表面的下 a 21. /種計算裝置，包括： 處理單元，包括處理器與邏輯單元；以及 功能單元，包括至少一記憶體晶片， =所斜隸置更包括㈣贿裝，所述半導體封 装包括· 下部半導體封裝，包括至少—半導體 包覆層，位於所述下部半導:面 所述 Ο 導電柱，位於所述下部半 ， 導雷妇沾古命把从 干^體封褒的上表面上， 導電柱的回度低於所述包覆層的上表面 上部半導體封裝，經由一 接至所述下部半導體封裝的所述=以扇人結構的形式連 32
TW099110562A 2009-05-08 2010-04-06 Package on package to prevent circuit pattern lift defect and method of fabricating the same TW201044548A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090040290A KR20100121231A (ko) 2009-05-08 2009-05-08 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법

Publications (1)

Publication Number Publication Date
TW201044548A true TW201044548A (en) 2010-12-16

Family

ID=43061861

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099110562A TW201044548A (en) 2009-05-08 2010-04-06 Package on package to prevent circuit pattern lift defect and method of fabricating the same

Country Status (4)

Country Link
US (1) US8253232B2 (zh)
JP (1) JP5566161B2 (zh)
KR (1) KR20100121231A (zh)
TW (1) TW201044548A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490531B2 (en) 2017-09-20 2019-11-26 Toshiba Memory Corporation Manufacturing method of semiconductor device and semiconductor device
TWI788995B (zh) * 2020-09-04 2023-01-01 美商美光科技公司 接合至一多層基板之一內層之表面附著裝置

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5207868B2 (ja) * 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
US8405197B2 (en) * 2009-03-25 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with stacked configuration and method of manufacture thereof
KR101624973B1 (ko) * 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
KR20130007602A (ko) * 2010-03-18 2013-01-18 모사이드 테크놀로지스 인코퍼레이티드 오프셋 다이 스태킹의 멀티-칩 패키지 및 그 제조 방법
US8963312B2 (en) * 2010-05-11 2015-02-24 Xintec, Inc. Stacked chip package and method for forming the same
KR101185457B1 (ko) * 2011-01-07 2012-10-02 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지 및 그 제조 방법
KR101239458B1 (ko) * 2011-01-25 2013-03-06 하나 마이크론(주) 계단식 적층구조를 갖는 반도체 패키지 및 그의 제조방법
KR20120129286A (ko) * 2011-05-19 2012-11-28 에스케이하이닉스 주식회사 적층 반도체 패키지
KR20130090173A (ko) * 2012-02-03 2013-08-13 삼성전자주식회사 반도체 패키지
TWI467731B (zh) * 2012-05-03 2015-01-01 矽品精密工業股份有限公司 半導體封裝件及其製法
KR101398811B1 (ko) 2012-05-31 2014-05-27 에스티에스반도체통신 주식회사 웨이퍼 레벨 패키지 및 그 제조방법
KR102029804B1 (ko) * 2012-12-17 2019-10-08 엘지이노텍 주식회사 패키지 온 패키지형 반도체 패키지 및 그 제조 방법
US9027226B2 (en) * 2013-03-27 2015-05-12 Bae Systems Information And Electronic Systems Integration Inc. Method for implementing prompt dose mitigating capacitor
US9691745B2 (en) * 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
KR20150014701A (ko) * 2013-07-30 2015-02-09 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9252076B2 (en) 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9324698B2 (en) 2013-08-13 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
TWI646639B (zh) 2013-09-16 2019-01-01 Ｌｇ伊諾特股份有限公司 半導體封裝
KR102093927B1 (ko) * 2013-09-27 2020-03-26 엘지이노텍 주식회사 반도체 패키지
KR102091619B1 (ko) * 2013-09-27 2020-03-23 엘지이노텍 주식회사 반도체 패키지
KR102084540B1 (ko) * 2013-10-16 2020-03-04 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102258739B1 (ko) 2014-03-26 2021-06-02 삼성전자주식회사 하이브리드 적층 구조를 갖는 반도체 소자 및 그 제조방법
KR102262907B1 (ko) * 2014-05-30 2021-06-09 삼성전기주식회사 패키지 기판, 패키지, 적층 패키지 및 패키지 기판 제조 방법
KR102270283B1 (ko) * 2014-11-11 2021-06-29 엘지이노텍 주식회사 반도체 패키지
KR101619460B1 (ko) * 2014-11-18 2016-05-11 주식회사 프로텍 적층형 반도체 패키지의 제조장치
KR102296746B1 (ko) * 2014-12-31 2021-09-01 삼성전자주식회사 적층형 반도체 패키지
KR102436220B1 (ko) * 2015-09-18 2022-08-25 삼성전기주식회사 패키지 기판 및 그 제조방법
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
CN107579061B (zh) 2016-07-04 2020-01-07 晟碟信息科技（上海）有限公司 包含互连的叠加封装体的半导体装置
CN107611099B (zh) * 2016-07-12 2020-03-24 晟碟信息科技（上海）有限公司 包括多个半导体裸芯的扇出半导体装置
KR102059403B1 (ko) * 2016-10-04 2019-12-26 삼성전자주식회사 팬-아웃 반도체 패키지
US10134716B2 (en) * 2017-03-16 2018-11-20 Intel Corporatin Multi-package integrated circuit assembly with through-mold via
CN108695284A (zh) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
JP2019161095A (ja) * 2018-03-15 2019-09-19 東芝メモリ株式会社 半導体装置
JP2019204841A (ja) * 2018-05-22 2019-11-28 株式会社村田製作所 半導体装置
JP2020047793A (ja) * 2018-09-19 2020-03-26 株式会社東芝 半導体装置の製造方法
KR102573307B1 (ko) 2018-09-28 2023-08-31 삼성전자 주식회사 반도체 패키지
KR102589684B1 (ko) * 2018-12-14 2023-10-17 삼성전자주식회사 반도체 패키지
KR102628536B1 (ko) * 2019-02-01 2024-01-25 에스케이하이닉스 주식회사 적층 칩 구조를 가지는 반도체 패키지
KR20210000812A (ko) * 2019-06-25 2021-01-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20210019226A (ko) * 2019-08-12 2021-02-22 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20210077290A (ko) * 2019-12-17 2021-06-25 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
US11942459B2 (en) 2022-02-14 2024-03-26 Western Digital Technologies, Inc. Semiconductor device package with exposed bond wires

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100386061B1 (ko) * 1995-10-24 2003-08-21 오끼 덴끼 고오교 가부시끼가이샤 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임
FI962816A (fi) * 1996-07-11 1998-01-12 Nokia Mobile Phones Ltd Mikropiirimodulien kotelorakenne
JP3564311B2 (ja) * 1999-01-27 2004-09-08 新光電気工業株式会社 柱状電極付き半導体ウエハの製造方法及び半導体装置の製造方法
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
JP2004172157A (ja) * 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP4057921B2 (ja) * 2003-01-07 2008-03-05 株式会社東芝 半導体装置およびそのアセンブリ方法
KR100604821B1 (ko) * 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
KR100546374B1 (ko) * 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
KR20050027384A (ko) 2003-09-15 2005-03-21 삼성전자주식회사 재배선 패드를 갖는 칩 사이즈 패키지 및 그 적층체
DE10360708B4 (de) * 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
US7378342B2 (en) * 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
JP4503462B2 (ja) * 2005-02-17 2010-07-14 株式会社フジクラ 半導体装置の製造方法
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
TWI321838B (en) 2006-11-08 2010-03-11 Advanced Semiconductor Eng Stacked type chip package, chip package and process thereof
KR100842915B1 (ko) 2007-01-17 2008-07-02 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
JP2008270597A (ja) * 2007-04-23 2008-11-06 Toshiba Corp 半導体装置
US7868455B2 (en) * 2007-11-01 2011-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Solving via-misalignment issues in interconnect structures having air-gaps
US7911070B2 (en) * 2008-09-25 2011-03-22 Stats Chippac Ltd. Integrated circuit packaging system having planar interconnect
US7863109B2 (en) * 2008-12-05 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490531B2 (en) 2017-09-20 2019-11-26 Toshiba Memory Corporation Manufacturing method of semiconductor device and semiconductor device
TWI684222B (zh) * 2017-09-20 2020-02-01 日商東芝記憶體股份有限公司 半導體裝置之製造方法
TWI788995B (zh) * 2020-09-04 2023-01-01 美商美光科技公司 接合至一多層基板之一內層之表面附著裝置
US11723150B2 (en) 2020-09-04 2023-08-08 Micron Technology, Inc. Surface mount device bonded to an inner layer of a multi-layer substrate

Also Published As

Publication number Publication date
US20100283140A1 (en) 2010-11-11
JP2010263192A (ja) 2010-11-18
US8253232B2 (en) 2012-08-28
JP5566161B2 (ja) 2014-08-06
KR20100121231A (ko) 2010-11-17

Similar Documents

Publication Publication Date Title
TW201044548A (en) Package on package to prevent circuit pattern lift defect and method of fabricating the same
EP2654388B1 (en) Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package
US7663250B2 (en) Wafer level package and manufacturing method thereof
TWI392066B (zh) 封裝結構及其製法
JP6027966B2 (ja) エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ
TWI453840B (zh) 半導體元件的製造方法
CN103620762B (zh) 半导体装置
TWI496254B (zh) 嵌埋半導體元件之封裝結構及其製法
US20110115085A1 (en) Semiconductor device and method of fabricating the same
KR100656587B1 (ko) 금속 포스트를 매개로 연결된 적층 기판을 이용한 적층패키지
JP4221193B2 (ja) 半導体パッケージ及びその製造方法
JP2008532292A5 (zh)
TWI500130B (zh) 封裝基板及其製法暨半導體封裝件及其製法
TW201218334A (en) Package substrate and fabrication method thereof
CN104396008B (zh) 半导体封装衬底、使用半导体封装衬底的封装系统及用于制造封装系统的方法
JP5404513B2 (ja) 半導体装置の製造方法
TW200952143A (en) Package substrate having embedded photosensitive semiconductor chip and fabrication method thereof
TWI336516B (en) Surface structure of package substrate and method for manufacturing the same
TWI578472B (zh) 封裝基板、半導體封裝件及其製法
TWI712147B (zh) 電子封裝件及其製法
KR20080048311A (ko) 반도체 패키지 및 그 제조방법
US9357646B2 (en) Package substrate
TWI389296B (zh) 可堆疊式封裝結構及其製造方法及半導體封裝結構
TWM462947U (zh) 封裝基板
TWI418006B (zh) 單層線路之封裝基板及其製法暨封裝結構