JP2009507431A - 高速用途においてパラレルデータをシリアルデータに変換する方法および装置 - Google Patents

高速用途においてパラレルデータをシリアルデータに変換する方法および装置 Download PDF

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JP2009507431A
JP2009507431A JP2008529341A JP2008529341A JP2009507431A JP 2009507431 A JP2009507431 A JP 2009507431A JP 2008529341 A JP2008529341 A JP 2008529341A JP 2008529341 A JP2008529341 A JP 2008529341A JP 2009507431 A JP2009507431 A JP 2009507431A
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data
bit
buses
bus
receiving
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JP2008529341A
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Japanese (ja)
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JP2009507431A5 (enExample
Inventor
モーザノ，クリストファー，ケイ．
リー，ウェン
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マイクロン テクノロジー， インク．
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Publication of JP2009507431A publication Critical patent/JP2009507431A/ja
Publication of JP2009507431A5 publication Critical patent/JP2009507431A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Bus Control (AREA)
  • Electronic Switches (AREA)
JP2008529341A 2005-09-01 2006-08-31 高速用途においてパラレルデータをシリアルデータに変換する方法および装置 Pending JP2009507431A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/218,997 US7358872B2 (en) 2005-09-01 2005-09-01 Method and apparatus for converting parallel data to serial data in high speed applications
PCT/US2006/034356 WO2007028095A2 (en) 2005-09-01 2006-08-31 Method and apparatus for converting parallel data to serial data in high speed applications

Publications (2)

Publication Number Publication Date
JP2009507431A true JP2009507431A (ja) 2009-02-19
JP2009507431A5 JP2009507431A5 (enExample) 2009-07-23

Family

ID=37690564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008529341A Pending JP2009507431A (ja) 2005-09-01 2006-08-31 高速用途においてパラレルデータをシリアルデータに変換する方法および装置

Country Status (9)

Country Link
US (4) US7358872B2 (enExample)
EP (2) EP2287848A1 (enExample)
JP (1) JP2009507431A (enExample)
KR (1) KR20080050461A (enExample)
CN (1) CN101258555A (enExample)
AT (1) ATE491206T1 (enExample)
DE (1) DE602006018764D1 (enExample)
TW (1) TW200723713A (enExample)
WO (1) WO2007028095A2 (enExample)

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JP2010287301A (ja) * 2009-06-09 2010-12-24 Hynix Semiconductor Inc 半導体メモリ装置のデータ整列回路
JP2014049173A (ja) * 2012-09-04 2014-03-17 Toshiba Corp 半導体記憶装置

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US8004446B2 (en) * 2007-02-28 2011-08-23 Panasonic Corporation A/D converter and A/D conversion method
US7956644B2 (en) * 2007-05-10 2011-06-07 Qimonda Ag Peak power reduction using fixed bit inversion
US9354890B1 (en) 2007-10-23 2016-05-31 Marvell International Ltd. Call stack structure for enabling execution of code outside of a subroutine and between call stack frames
US9442758B1 (en) 2008-01-21 2016-09-13 Marvell International Ltd. Dynamic processor core switching
US8243543B2 (en) * 2008-02-29 2012-08-14 Hynix Semiconductor Inc. Semiconductor memory device for high-speed data input/output
KR100929831B1 (ko) * 2008-02-29 2009-12-07 주식회사 하이닉스반도체 고속의 데이터 입출력을 위한 반도체 메모리 장치
KR100948069B1 (ko) * 2008-09-10 2010-03-16 주식회사 하이닉스반도체 데이터 출력 회로
JP4992938B2 (ja) * 2009-05-27 2012-08-08 富士通株式会社 パラレル−シリアル変換器
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
US8217814B1 (en) * 2010-12-17 2012-07-10 Mosys, Inc. Low power serial to parallel converter
CN102315852B (zh) * 2011-05-03 2014-07-30 四川和芯微电子股份有限公司 并串数据转换电路及并串数据转换系统
JP2012257047A (ja) * 2011-06-08 2012-12-27 Fujitsu Ltd パラレルシリアル変換回路、情報処理装置及び情報処理システム
US9098694B1 (en) * 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic
US8767463B2 (en) * 2011-08-11 2014-07-01 Smart Modular Technologies, Inc. Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof
US9530461B2 (en) * 2012-06-29 2016-12-27 Intel Corporation Architectures and techniques for providing low-power storage mechanisms
US8823558B2 (en) 2012-08-30 2014-09-02 International Business Machines Corporation Disparity reduction for high speed serial links
US9405538B2 (en) * 2012-12-28 2016-08-02 Intel Corporation Functional unit having tree structure to support vector sorting algorithm and other algorithms
US9448965B2 (en) 2013-03-15 2016-09-20 Micron Technology, Inc. Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
CN104881390B (zh) * 2015-05-11 2018-02-27 杭州紫来测控技术有限公司 通过串行并行总线相互转换以减少线缆数量的方法
CN106095574B (zh) * 2016-06-13 2019-01-08 北京唯智佳辰科技发展有限责任公司 海量计算粗颗粒并行实现及计算任务随机动态分配方法
US10658041B1 (en) * 2018-11-30 2020-05-19 Micron Technology, Inc. Apparatus and methods for serializing data output
US11789835B2 (en) * 2020-11-20 2023-10-17 Micron Technology, Inc. Test input/output speed conversion and related apparatuses and methods
MY205100A (en) * 2020-12-29 2024-10-02 Skyechip Sdn Bhd A generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

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JPH08340259A (ja) * 1995-06-13 1996-12-24 Mitsubishi Electric Corp 並直列変換回路
JP2002009629A (ja) * 2000-06-23 2002-01-11 Nec Miyagi Ltd パラレルシリアル変換回路
JP2002152053A (ja) * 2000-11-08 2002-05-24 Nec Microsystems Ltd パラレル−シリアル変換回路

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JPH08340259A (ja) * 1995-06-13 1996-12-24 Mitsubishi Electric Corp 並直列変換回路
JP2002009629A (ja) * 2000-06-23 2002-01-11 Nec Miyagi Ltd パラレルシリアル変換回路
JP2002152053A (ja) * 2000-11-08 2002-05-24 Nec Microsystems Ltd パラレル−シリアル変換回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010287301A (ja) * 2009-06-09 2010-12-24 Hynix Semiconductor Inc 半導体メモリ装置のデータ整列回路
JP2014049173A (ja) * 2012-09-04 2014-03-17 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
US20070046511A1 (en) 2007-03-01
DE602006018764D1 (de) 2011-01-20
EP1938329A2 (en) 2008-07-02
ATE491206T1 (de) 2010-12-15
KR20080050461A (ko) 2008-06-05
US20080136690A1 (en) 2008-06-12
WO2007028095A3 (en) 2007-06-14
US20100289678A1 (en) 2010-11-18
US7764206B2 (en) 2010-07-27
EP2287848A1 (en) 2011-02-23
US7358872B2 (en) 2008-04-15
EP1938329B1 (en) 2010-12-08
WO2007028095A2 (en) 2007-03-08
CN101258555A (zh) 2008-09-03
US7525458B2 (en) 2009-04-28
TW200723713A (en) 2007-06-16
US20090201746A1 (en) 2009-08-13

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