Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
  • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M9/00—Parallel/series conversion or vice versa
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
  • G11C2207/10—Aspects relating to interfaces of memory device to external buses
  • G11C2207/107—Serial-parallel conversion of data or prefetch

Definitions

• the present invention relates generally to parallel-to-serial conversion and, more
• SDRAM Secure Digital RAM
• An SDRAM device generally includes a memory array comprising a large number of memory cells each configured
• DQPAD data pad
• the SDRAM is generally based on a common clock signal. 5
• DDR generation SDRAM devices are generally configured such that data from the memory cells may be accessed and one bit of data may be output to the DQPAD on every clock cycle.
• DDR double data rate
• DDR SDRAM devices generally allow for two bits of data to be accessed and output to the DQPAD on every clock cycle. To achieve this, DDR SDRAM devices commonly clock data out to the DQPAD on every rising and every falling edge of the clock signal.
• DDR SDRAMS generally allow for data to be transferred from the memory device at a clock rate in - ⁇ -the range of 200 to 550MHz.
• the next generation of SDRAMS include DDR2 SDRAMS.
• the advantage of DDR2 is the advantage of DDR2
• DDR2 will transfer data on every rising and falling edge of the clock, achieving an
• DDR2's clock frequency is further boosted by an improved electrical interface running twice as fast as the memory clock, on-die termination, pre-fetch buffers and off-chip drivers.
• DDR2 devices have a data transfer
• the present invention may address one or more of the problems set forth above.
• Fig.1 illustrates a block diagram of an exemplary processor-based device
• Fig. 2 illustrates a block diagram of an exemplary memory device which may be
• Fig. 3 illustrates a block diagram of an exemplary parallel-to-serial converter in
• Fig. 4 is a schematic diagram of a switch which may be employed in the parallel-to- serial converter in accordance with embodiments of the present invention
• Fig. 5 is a schematic diagram of a switching element which may be employed in the
• - Fig. 6 is a schematic diagram of-a clock generator circuit configured to control the
• Fig. 7 is a schematic diagram of a sub-data pipeline in the parallel-to-serial converter in accordance with embodiments of the present invention.
• Fig. 8 is a schematic diagram of a pointer control circuit for controlling portions of
• Fig. 9 is a timing diagram illustrating control and data signals in accordance with
• FIG. 1 a block diagram
• the device 10 may be any of a variety of different types, such as
• a processor 12 such as a microprocessor
• the device 10 typically includes a power supply 14. For instance, if the device 10
• the power supply 14 would advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries.
• the power supply 14 may also include an A/C adapter, so that the device may be plugged into a wall outlet, for instance.
• the power supply 14 may also include a D/C adapter, so that the device 10 may be plugged into a vehicle's cigarette lighter, for instance.
• a user interface 16 may be coupled to the processor 12.
• the user interface 16 may include an input device, such as buttons, switches, a keyboard, a light pin, a mouse, and/or a voice recognition system, for instance.
• a display 18 may also be coupled to the processor 12.
• the display 18 may include an LCD display, a CRT, LEDs, and/or an audio display. Furthermore, an RF
• subsystem/baseband processor 20 may also be coupled to the processor 12.
• subsystem/baseband processor 20 may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown).
• a communication port 22 may also be
• the communication port 22 may be adapted to be coupled to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a peripheral device 24, such as
• network such as a local area network or the Internet.
• memory is coupled to the processor 12 to store and facilitate execution of the software program.
• the processor 12 may be any type of processor
• volatile memory 26 which may include dynamic random access memory
• DRAM dynamic random access memory
• SRAM static random access memory
• DDR Double Data Rate
• the processor 12 may also be coupled to non- volatile memory 28,
• the non-volatile memory 28 may include a read only memory (ROM), such as an EPROM or Flash Memory, to be used in conjunction with the volatile memory.
• ROM read only memory
• the size of the ROM is typically selected to be just large enough to store any necessary operating system,
• the volatile memory 26 is typically quite large so thatit can store dynamically loaded applications.
• the non-volatile memory 28 may include a high capacity memory such as a disk drive, tape
• CD ROM drive CD ROM drive
• DVD read/write CD ROM drive
• floppy disk drive CD ROM drive
• the volatile memory 26 may include a number of SDRAMs which may implement
• the SDRAM differs from a
• the DRAM in that the SDRAM is controlled synchronously with a timing source, such as the system clock.
• a timing source such as the system clock.
• latches are used to provide data and other information on the inputs and outputs of the SDRAM.
• the processor 12 may access a data output latch a predetermined number of clock cycles after issuing the read request.
• the predetermined number of clock cycles typically corresponds to the amount of time needed to access the requested data, move the data to the output latch, and allow the data to stabilize.
• the data is clocked out of the output latch synchronous with the system clock which provides the timing source for the processor 12.
• Synchronization of the data read from the output latch with the system clock is generally implemented via a delay locked loop (DLL) circuit.
• the DLL locks the data output signal to the system clock by shifting the output data in time such that it is nominally aligned with the system clock.
• the DLL can compensate for timing delays introduced by various components in the SDRAM.
• Write operations also are performed synchronously or in synchronization with a timing source, such as the system clock or other externally provided timing source.
• a timing source such as the system clock or other externally provided timing source.
• data may be clocked into an input latch and written to the memory array under control of a write clock provided from the external device which is performing the write operation.
• Delay locked loops may also be implemented to synchronize write data with the write clock.
• FIG. 2 a block diagram depicting an exemplary embodiment of an
• the SDRAM 30 may be a DDR3 SDRAM for example.
• the present technique may not be limited to DDR3 SDRAMs, and may be equally applicable to other synchronous memory devices, and particularly to other high speed memory
• Control, address, and data information provided over a memory bus are represented by individual inputs to the SDRAM 30. These individual representations are illustrated by a data bus 32, address lines 34, and various discrete lines directed to control logic 36. As will be appreciated, the various buses and control lines may vary depending on
• the SDRAM 30 includes a memory array 38 which comprises rows and columns of addressable memory cells. Each memory cell in a row is " coupled to a word line. Additionally, each memory cell in a column is coupled to a bit line. Each cell in the memory array 38 typically includes a storage capacitor and an access transistor as is conventional in the art.
• the SDRAM 30 interfaces with, for example, a processor 12, such as a microprocessor, through address lines 34 and data lines 32.
• a processor 12 such as a microprocessor
• an SDRAM controller may interface with other devices, such as an SDRAM controller, a microcontroller, a chip
• the microprocessor 12 also may provide a number of control signals to the SDRAM 30. Such signals may include row and column address
• strobe signals RAS and CAS a write enable signal WE, a clock enable signal CKE, and
• the control logic 36 controls the many available functions of the SDRAM 30. In addition, various other control circuits and signals not
• a row address buffer 40 and a row decoder 42 receive and decode row addresses
• the row decoder 42 typically includes a word line driver, an address decoder tree, and circuitry which translates a given row address received from row address buffers 40 and selectively activates the appropriate word line of the memory array 38 via the word line drivers.
• a column address buffer 44 and a column decoder 46 receive and decode column address signals provided on the address lines 34.
• the column decoder 46 may also determine when a column is defective, as well as the address of a replacement column.
• the column decoder 46 is coupled to sense amplifiers 48.
• the sense amplifiers 48 are the sense amplifiers 48.
• the sense amplifiers 48 are coupled to data-in (i.e., write) and data-out (i.e., read) circuitry.
• the data in circuitry may comprise a serial-to-parallel converter 50 configured to receive write data.
• the serial-to-parallel converter 50 includes data drivers and latches
• bus 51 provides data to the serial-to-parallel converter 50.
• the write data bus 51 is part of the databus 32.
• the sense amplifier 48 receives data from the
• serial-to-parallel converter 50 stores the data in the memory array 38 as a charge on a
• the write data bus 51 is an 8-bit data bus carrying data at 400MHz or higher.
• the SDRAM 30 transfers data to the microprocessor 12 from the memory array 38. Complementary bit lines for the accessed cell are equilibrated
• the sense amplifier 48 detects and amplifies a difference in " voltage between the complementary bit lines. Address information received on address lines 34 selects a subset of the bit lines and couples them to complementary pairs of
• I/O wires or lines input/output wires or lines.
• the I/O wires pass the amplified voltage signals to the
• the internal data-bus 54 is a parallel data bus that operates at a lower frequency (e.g.
• the parallel-to-serial converter 52 is configured to receive parallel data from the slower internal data bus 54 and to transmit the data, serially, to a data pad (DQPAD) 56 via the read data bus 58, As with the write data bus 51, the read data bus 58 is a high speed data
• SDRAM 30 introduces a number of design challenges. As described further below,
• embodiments of the present invention may be implemented within the parallel-to-serial converter 52 such that the SDRAM 30 is capable of accurately operating at the high
• the parallel-to-serial converter 52 may include a data pipeline to receive parallel data from the sense amplifier 48, via the internal data bus 54,
• the DQPAD 56 provides a mechanism for routing the data to a requesting device (such as the processor 12) or any other component in the system 10.
• parallel-to-serial converter 52 may be provided by a delay locked loop (DLL) circuit 60 which provides a shifted clock signal (DLLCK) which is synchronous with the external DLL circuit 60
• FIG. 3 a more detailed block diagram of the parallel-to-serial
• the parallel-to-serial converter 52 receives parallel
• the internal data bus 54 receives data from the sense amplifiers 48 via the internal data bus 54.
• the internal data bus 54 receives data from the sense amplifiers 48 via the internal data bus 54.
• the internal data bus includes individual parallel data buses.
• the internal data bus includes individual parallel data buses.
• the internal data bus includes individual parallel data buses.
• data bus 54 is configured to carry one bit of data at a time to the parallel-to-serial converter 52. As will become evident through the discussion below, the data bits are
• the read data bus 58 is a serial data bus
• the internal data bus 54 is a parallel data bus.
• the presently described parallel-to-serial converter receives the data on the much slower, but parallel, internal data bus 54 and outputs the data onto the read data bus 58 in a serial fashion and at a much
• the parallel-to-serial converter 52 includes a data pipeline 62 and binary data sort logic 64.
• the data pipeline 62 includes a number of sub-data pipelines 66, Generally, each of the sub-data
• pipelines 66 is responsible for outputting a single bit of data at a time to the binary data sort logic 64 under the control of the control signals IN ⁇ 0:2> OUT ⁇ 0:2> and RST.
• the generation of the control signals of the data pipeline 62 is described in more detail with
• those individual data lines carrying the second four bits (upper level) of data from the data word also include a data
• Each of the data latches 68 is controlled by a trap enable signal TRP.
• the generation of the trap enable signal TRP will be discussed further below with respect to Fig. 7.
• the binary data sort logic 64 includes a plurality of switches 70 and a final stage
• Each of the switches 70 operates under the control of a respective internally generated switch control signals RCK ⁇ 0>, RCK ⁇ 1>, RCK ⁇ 2>, FCK ⁇ 0>, FCK ⁇ 1> or FCK ⁇ 2>.
• Switch control signals RCK ⁇ 0>, RCK ⁇ 1> and RCK ⁇ 2> are
• each of the switches 70 simply toggles between two data inputs. That is
• each of the switches 70 actually passes the inverse of the incoming data.
• references to data passed by the inverters 70 is simply illustrated and described as passing the data
• the switch 70 immediately below this switch, toggles between passing the data d2 and passing the data ⁇ under the control of the switch control signal RCK ⁇ 2>, and so forth.
• the first four switches (i.e., thefour leftmost switches inTig. 3) ⁇ receive input directly from the data pipeline 62. These first four switches 70 make up the "first stage"
• the last stage switching logic 72 receives outputs 74A and 74B and toggles data directly to the DQPAD 56 via read data bus 58 under the control of the DLL
• the last stage switching logic 72 performs the same function as the switches 70 (i.e., toggling between two inputs), but provides for the inclusion of an output enable signal (QED) to enable the operation of the binary data sort logic 64.
• QED output enable signal
• stage switching logic 72 will be described in more detail with respect to Fig. 5, below.
• data sort logic 64 essentially doubles the data transmission frequency such that the parallel
• the data transmitted from the bus 54 is passed to the read data bus 58 and that the read data bus 58 operates at approximately 8X the frequency of the internal bus 54.
• the data on the read data bus 58 is being transmitted serially and driven at a rate that matches the external clock (XCLK) rate and the DLL clock (DLLCK) rate.
• XCLK external clock
• DLLCK DLL clock
• the switch 70 is configured to switch between two inputs
• SWITCH INPUT 1 AND SWITCH INPUT 2 under the control of a switch control
• the switch 70 includes four N-channel transistors 76 and four P-channel transistors 78 configured as illustrated in Fig. 4.
• the output terminal (SWITCH OUTPUT) is the inverse of SWITCH INPUT 1.
• the switch control signal CK When the switch control signal CK is high, the switch flips such that the SWITCH OUTPUT receives SWITCH INPUT 2.
• the SWITCH OUTPUT is the inverse of the selected input.
• FIG. 4 may be described in accordance with the block diagram previously
• the switch 70 switches between SWITCH INPUT 1 (here, d ⁇ ) and SWITCH INPUT 2 (here, d4) under the control of the switch control signal CK (here, RCK ⁇ 1>)
• switch 70 toggles between two input signals based on one or more control signals.
• the switching circuit 72 toggles between the input received on bus 74A and the input received on bus 74B (illustrated in Fig. 3)
• an output enable signal QED may be implemented to facilitate data transmission to the DQPAD 56 on each of the rising and falling edges of the DLLCK signal. Accordingly, to combine the
• the switch 70 of the last stage switching logic 72 generally operates as previously
• a second switch 70 also operating under the control of DLLCK toggles
• the final stage switching circuit 72 may also include a
• the final stage switching circuit 72 toggles between outputting the data
• the clock generator circuit 100 may be implemented to internally generate the switch control signals RCK ⁇ 0>, RCK ⁇ 1>, RCK ⁇ 2> FCK ⁇ 0>, FCK ⁇ 1> and FCK ⁇ 2>.
• control signals is essentially generated from the DLLCK signal received from the DLL 60 (Fig. 2).
• the exemplary clock generation circuit As with the last stage switching logic 72, the exemplary clock generation circuit
• the clock generation circuit 100 also receives a data enable signal QED such that generation of the switching control signals is only conducted when the QED signal is asserted.
• the clock generation circuit 100 includes a number of flip flops 102 configured to latch data to their respective
• the clock generation circuit 100 includes a number of inverters 104 to provide inversion of incoming signals. Further, the clock generation circuit 100 includes a latch 106 which
• circuit 100 is simply provided to generate the switch control signals RCK ⁇ 0>, RCK ⁇ 1>,
• the binary data sort logic 64 for controlling the first and second stages of the binary data
• each of the switch control signals is generated from only the DLLCK signal through the logic provided in the clock generation logic 100. The relationship
• each sub-data pipeline circuit 66 is simply configured to latch data bits in order from the read data bus 58 to the binary data
• the sub-data pipeline circuit 66 For illustrative purposes, the sub-data pipeline circuit 66
• Fig. 7 is illustrated as receiving the data d4 (Fig. 3). This represents the second parallel
• the sub-data pipeline circuit 66 includes three storage latches 108 employed for slow cycle, high latency.
• latches 108 may be first in first out (FIFO) storage devices for instance.
• the latches 108 receive an input signal (here, the data signal d4) through a timing control block 110 under
• the input control signal IN ⁇ 0:2> traps data in the respective latch 108 and the signal OUT ⁇ 0:2> switches the data
• the IN ⁇ 0:2> signals are self-timed and are faster than the data. These input control signals arrive before the data.
• the OUT ⁇ 0:2> control signals are based off of the DLLCK
• the timing control circuit 110 is implemented to hold valid data and convert pre- charged data to DC to smooth timing from remote (versus close) data.
• the timing control is implemented to hold valid data and convert pre- charged data to DC to smooth timing from remote (versus close) data.
• the timing control circuit 110 includes three NOR gates 112, two inverters 114 and an AND gate 116, which may be arranged as illustrated in Fig. 7.
• the timing control circuit 110 is provided to help with timing differences between data bits arriving from memory locations close to the parallel-to-serial converter 52, versus data ' bits arriving ffo ⁇ n more distant memory locations. As will be appreciated, the data bits arrive as pulses. The timing is generally defaulted to match with either the closer memory locations or the more distant memory locations. For instance, data arriving from a memory location very close to the parallel-to-
• serial converter 52 may have a short pulse and something very far away may have a long
• the timing control circuit 110 traps the pulse and aligns the timing from all of the different areas of the memory array 38.
• the reset signal RST is also gated into the timing
• control circuit 110 to reset the latch through the lower gate.
• the RST signal aids in
• the data latch 68 (Fig. 3). As previously described, the data latch 68 is employed to temporarily trap the upper bits of the incoming eight bit data
• the TRP signal is generated by combining the switch control signals RCK ⁇ 0>, RCK ⁇ 1> and FCK ⁇ 0> using a NAND
• An inverter 120 may also be employed to ensure proper polarity of the trapper control signal TRP. This allows the switching of OUT ⁇ 0;2> to have half a data byte cycle
• the circuit 122 includes flip-flops 124 which operate - under the control of the switch control signal FCK ⁇ 0> and its inverse, as illustrated in Fig. 8.
• the first flip-flop 124 is a reset (R) flip-flop, while the second and third flip-flops 124 are set (S) flip-flops.
• An inverter 126 may be
• switch control signal FCK ⁇ 0> is based off of the DLLCK signal, the output control signals OUT ⁇ 0:2> are also derived from the DLLCK signal. As illustrated in Fig. 8, the
• circuit 122 may be employed to generate the output control signals OUT ⁇ 0:2> employed to latch data out of the sub-data pipelines 66.
• Fig. 9 a timing diagram of the external clock signal XCLK, the
• FCK ⁇ 0:2> FCK ⁇ 0:2>.
• the DLLCK signal operates at the same speed as
• the XCLK signal but slightly ahead of it to compensate for signal delays.
• the RCK ⁇ 0> and FCK ⁇ 0> signals are running at about half the speed of the DLLCK
• the switch 70 under the control of RCK ⁇ 1> always toggles between transmitting input data d0 and d4. That is, the switch 70, under the control of RCK ⁇ 1> alternatingly transmits the data d0 and d4 through the switch 70. Similarly, the switch 70 under the control of RCK ⁇ 2> toggles between input d2 and d6. The switch 70, under the controhof FCK ⁇ 1>, always toggles between data input dl and d5. Finally, the switch 70 under the control of FCK ⁇ 2> always toggles between
• the signal RCK ⁇ 0> toggles between transmitting the data d ⁇ , d2, d4 and do, in that order, based on the configuration illustrated and described with reference to Fig, 3. That is, the
• switch 70 controlled by the signal RCK ⁇ 0> alternatingly transmits the data d ⁇ , d2, d4 and
• each slower stage uses the extra time as set up time for the data. For example RCK ⁇ 0>
• embodiments of the present invention provide techniques for converting parallel data to serial data in high speed applications, such as high speed
• the conversion is performed by employing a number of switches in the converter. Further, the

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