TW200723713A - Method and apparatus for converting parallel data to serial data in high speed applications - Google Patents

Method and apparatus for converting parallel data to serial data in high speed applications

Info

Publication number
TW200723713A
TW200723713A TW095132286A TW95132286A TW200723713A TW 200723713 A TW200723713 A TW 200723713A TW 095132286 A TW095132286 A TW 095132286A TW 95132286 A TW95132286 A TW 95132286A TW 200723713 A TW200723713 A TW 200723713A
Authority
TW
Taiwan
Prior art keywords
data
high speed
parallel data
speed applications
converting parallel
Prior art date
Application number
TW095132286A
Other languages
English (en)
Chinese (zh)
Inventor
Christopher K Morzano
Wen Li
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200723713A publication Critical patent/TW200723713A/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/107Serial-parallel conversion of data or prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Bus Control (AREA)
  • Electronic Switches (AREA)
TW095132286A 2005-09-01 2006-09-01 Method and apparatus for converting parallel data to serial data in high speed applications TW200723713A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/218,997 US7358872B2 (en) 2005-09-01 2005-09-01 Method and apparatus for converting parallel data to serial data in high speed applications

Publications (1)

Publication Number Publication Date
TW200723713A true TW200723713A (en) 2007-06-16

Family

ID=37690564

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095132286A TW200723713A (en) 2005-09-01 2006-09-01 Method and apparatus for converting parallel data to serial data in high speed applications

Country Status (9)

Country Link
US (4) US7358872B2 (enExample)
EP (2) EP2287848A1 (enExample)
JP (1) JP2009507431A (enExample)
KR (1) KR20080050461A (enExample)
CN (1) CN101258555A (enExample)
AT (1) ATE491206T1 (enExample)
DE (1) DE602006018764D1 (enExample)
TW (1) TW200723713A (enExample)
WO (1) WO2007028095A2 (enExample)

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US8243543B2 (en) * 2008-02-29 2012-08-14 Hynix Semiconductor Inc. Semiconductor memory device for high-speed data input/output
KR100929831B1 (ko) * 2008-02-29 2009-12-07 주식회사 하이닉스반도체 고속의 데이터 입출력을 위한 반도체 메모리 장치
KR100948069B1 (ko) * 2008-09-10 2010-03-16 주식회사 하이닉스반도체 데이터 출력 회로
JP4992938B2 (ja) * 2009-05-27 2012-08-08 富士通株式会社 パラレル−シリアル変換器
KR101027681B1 (ko) * 2009-06-09 2011-04-12 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 정렬 회로
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
US8217814B1 (en) * 2010-12-17 2012-07-10 Mosys, Inc. Low power serial to parallel converter
CN102315852B (zh) * 2011-05-03 2014-07-30 四川和芯微电子股份有限公司 并串数据转换电路及并串数据转换系统
JP2012257047A (ja) * 2011-06-08 2012-12-27 Fujitsu Ltd パラレルシリアル変換回路、情報処理装置及び情報処理システム
US9098694B1 (en) * 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic
US8767463B2 (en) * 2011-08-11 2014-07-01 Smart Modular Technologies, Inc. Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof
US9530461B2 (en) * 2012-06-29 2016-12-27 Intel Corporation Architectures and techniques for providing low-power storage mechanisms
US8823558B2 (en) 2012-08-30 2014-09-02 International Business Machines Corporation Disparity reduction for high speed serial links
JP2014049173A (ja) * 2012-09-04 2014-03-17 Toshiba Corp 半導体記憶装置
US9405538B2 (en) * 2012-12-28 2016-08-02 Intel Corporation Functional unit having tree structure to support vector sorting algorithm and other algorithms
US9448965B2 (en) 2013-03-15 2016-09-20 Micron Technology, Inc. Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
CN104881390B (zh) * 2015-05-11 2018-02-27 杭州紫来测控技术有限公司 通过串行并行总线相互转换以减少线缆数量的方法
CN106095574B (zh) * 2016-06-13 2019-01-08 北京唯智佳辰科技发展有限责任公司 海量计算粗颗粒并行实现及计算任务随机动态分配方法
US10658041B1 (en) * 2018-11-30 2020-05-19 Micron Technology, Inc. Apparatus and methods for serializing data output
US11789835B2 (en) * 2020-11-20 2023-10-17 Micron Technology, Inc. Test input/output speed conversion and related apparatuses and methods
MY205100A (en) * 2020-12-29 2024-10-02 Skyechip Sdn Bhd A generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

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Also Published As

Publication number Publication date
US20070046511A1 (en) 2007-03-01
DE602006018764D1 (de) 2011-01-20
EP1938329A2 (en) 2008-07-02
ATE491206T1 (de) 2010-12-15
KR20080050461A (ko) 2008-06-05
US20080136690A1 (en) 2008-06-12
WO2007028095A3 (en) 2007-06-14
US20100289678A1 (en) 2010-11-18
US7764206B2 (en) 2010-07-27
EP2287848A1 (en) 2011-02-23
US7358872B2 (en) 2008-04-15
EP1938329B1 (en) 2010-12-08
WO2007028095A2 (en) 2007-03-08
CN101258555A (zh) 2008-09-03
US7525458B2 (en) 2009-04-28
US20090201746A1 (en) 2009-08-13
JP2009507431A (ja) 2009-02-19

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