ATE498161T1 - Dma-verfahren, entsprechende system und rechnerprogrammprodukt - Google Patents

Dma-verfahren, entsprechende system und rechnerprogrammprodukt

Info

Publication number
ATE498161T1
ATE498161T1 AT02791783T AT02791783T ATE498161T1 AT E498161 T1 ATE498161 T1 AT E498161T1 AT 02791783 T AT02791783 T AT 02791783T AT 02791783 T AT02791783 T AT 02791783T AT E498161 T1 ATE498161 T1 AT E498161T1
Authority
AT
Austria
Prior art keywords
data
idma
dma
dma module
input buffer
Prior art date
Application number
AT02791783T
Other languages
English (en)
Inventor
Andrea Bragagnini
Antonio Varriale
Original Assignee
Telecom Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Spa filed Critical Telecom Italia Spa
Application granted granted Critical
Publication of ATE498161T1 publication Critical patent/ATE498161T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Circuits Of Receivers In General (AREA)
  • Stored Programmes (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Executing Machine-Instructions (AREA)
AT02791783T 2002-12-06 2002-12-06 Dma-verfahren, entsprechende system und rechnerprogrammprodukt ATE498161T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2002/013847 WO2004053708A1 (en) 2002-12-06 2002-12-06 A method for direct memory access, related architecture and computer program product

Publications (1)

Publication Number Publication Date
ATE498161T1 true ATE498161T1 (de) 2011-02-15

Family

ID=32479688

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02791783T ATE498161T1 (de) 2002-12-06 2002-12-06 Dma-verfahren, entsprechende system und rechnerprogrammprodukt

Country Status (7)

Country Link
US (1) US20060026307A1 (de)
EP (1) EP1570360B1 (de)
AT (1) ATE498161T1 (de)
AU (1) AU2002358100A1 (de)
CA (1) CA2504713C (de)
DE (1) DE60239166D1 (de)
WO (1) WO2004053708A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US10884712B1 (en) 2005-12-30 2021-01-05 The Mathworks, Inc. Component-based framework for generating device driver model elements
US9329840B1 (en) * 2005-12-30 2016-05-03 The Mathworks, Inc. Graphical programming of custom device drivers
DE102007012847A1 (de) 2007-03-17 2008-10-02 Christian-Albrechts-Universität Zu Kiel Navigations-, Ortungs-, Positionierungs-, Lokalisierungs- und Kommunikationsverfahren auf IDMA-Basis
JP2012243176A (ja) * 2011-05-23 2012-12-10 Renesas Electronics Corp 半導体装置及び制御方法
US8677044B1 (en) * 2012-10-25 2014-03-18 Qlogic, Corporation Method and system for communication using multiple DMA channels

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481578A (en) * 1982-05-21 1984-11-06 Pitney Bowes Inc. Direct memory access data transfer system for use with plural processors
US5212795A (en) * 1988-10-11 1993-05-18 California Institute Of Technology Programmable DMA controller
US5634099A (en) * 1994-12-09 1997-05-27 International Business Machines Corporation Direct memory access unit for transferring data between processor memories in multiprocessing systems
US5781799A (en) * 1995-09-29 1998-07-14 Cirrus Logic, Inc. DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
GB9802097D0 (en) * 1998-01-30 1998-03-25 Sgs Thomson Microelectronics DMA controller
US6182165B1 (en) * 1998-06-01 2001-01-30 Advanced Micro Devices, Inc. Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system
US6870929B1 (en) * 1999-12-22 2005-03-22 Juniper Networks, Inc. High throughput system for encryption and other data operations
US6691178B1 (en) * 2000-02-22 2004-02-10 Stmicroelectronics, Inc. Fencepost descriptor caching mechanism and method therefor
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
GB2372115A (en) * 2001-02-08 2002-08-14 Mitel Semiconductor Ltd Direct memory access controller
US20040010612A1 (en) * 2002-06-11 2004-01-15 Pandya Ashish A. High performance IP processor using RDMA

Also Published As

Publication number Publication date
CA2504713A1 (en) 2004-06-24
AU2002358100A1 (en) 2004-06-30
EP1570360A1 (de) 2005-09-07
CA2504713C (en) 2011-06-07
DE60239166D1 (de) 2011-03-24
WO2004053708A1 (en) 2004-06-24
US20060026307A1 (en) 2006-02-02
EP1570360B1 (de) 2011-02-09

Similar Documents

Publication Publication Date Title
CN109522052B (zh) 一种计算装置及板卡
DE502005008714D1 (de) Verfahren und vorrichtung zum zugriff auf daten eines botschaftsspeichers eines kommunikationsbausteins
TW200630901A (en) Image processing apparatus and image processing method
GB2434895A (en) The Buffered continous multi-drop clock rin
ATE454014T1 (de) Bilddatenstruktur für direkten speicherzugriff
TW200737201A (en) Multiple independent serial link memory
TW429347B (en) High-speed data transfer system including plurality of memory module and controller
DE502005008758D1 (de) Botschaftsverwalter und verfahren zur steuerung dees kommunikationsbausteins
CN107102964A (zh) 一种利用高速率连接器进行gpu集群拓展的方法
ATE478386T1 (de) Multimedia-kartenschnittstellenverfahren, computerprogrammprodukt und vorrichtung
ATE498161T1 (de) Dma-verfahren, entsprechende system und rechnerprogrammprodukt
SE0402098D0 (sv) A control system
ATE516566T1 (de) Datenübertragung zwischen modulen
ATE540342T1 (de) Serielles bussystem, teilnehmervorrichtung und an die teilnehmervorrichtung anschliessbare eingabe- /ausgabekarte
KR970068365A (ko) 통신제어장치 및 그것을 사용한 통신시스템
AU2001288553A1 (en) Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
ATE204660T1 (de) Datenfliessbandordnungssystem
RU139326U1 (ru) Вычислительный модуль
CN115568055A (zh) 一种氛围灯控制方法、控制器、电子设备及存储介质
CN111078624B (zh) 片上网络处理系统和片上网络数据处理方法
TW200511027A (en) Information processing apparatus, memory, information processing method, and program
TWI265409B (en) Method and structure of using one basic input/output system (BIOS) memory to start up a computer system
DE60005157D1 (de) Verfahren und anordnung für blockdatenübertragung
DE60211550D1 (de) Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus
Mohanty et al. A computer algorithm for determining optimal buffer size in a serial flow production system

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties