WO2008105053A1 - データ送信回路およびデータ送受信システム - Google Patents

データ送信回路およびデータ送受信システム Download PDF

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Publication number
WO2008105053A1
WO2008105053A1 PCT/JP2007/053534 JP2007053534W WO2008105053A1 WO 2008105053 A1 WO2008105053 A1 WO 2008105053A1 JP 2007053534 W JP2007053534 W JP 2007053534W WO 2008105053 A1 WO2008105053 A1 WO 2008105053A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
data transmission
data signal
signal
clock generation
Prior art date
Application number
PCT/JP2007/053534
Other languages
English (en)
French (fr)
Inventor
Hisakatsu Yamaguchi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009501054A priority Critical patent/JP4723029B2/ja
Priority to PCT/JP2007/053534 priority patent/WO2008105053A1/ja
Publication of WO2008105053A1 publication Critical patent/WO2008105053A1/ja
Priority to US12/546,166 priority patent/US7982638B2/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa

Abstract

 パラレルデータ信号をシリアルデータ信号に変換して送信するデータ送信回路は、データ転送レートの向上、製造ばらつきの増大および電源電圧や温度の変動などに拘わらず、内部要素間のデータ送受信を確実に実施するために、クロック発生回路、出力回路およびシフトレジスタ回路を備えて構成される。クロック発生回路は、クロック信号を発生させる。出力回路は、シリアルデータ信号を出力するために設けられる。シフトレジスタ回路は、パラレルデータ信号を取り込み、クロック発生回路のクロック信号に同期したシフト動作により、取り込んだパラレルデータ信号を出力回路にビット単位で順次転送する。
PCT/JP2007/053534 2007-02-26 2007-02-26 データ送信回路およびデータ送受信システム WO2008105053A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009501054A JP4723029B2 (ja) 2007-02-26 2007-02-26 データ送信回路およびデータ送受信システム
PCT/JP2007/053534 WO2008105053A1 (ja) 2007-02-26 2007-02-26 データ送信回路およびデータ送受信システム
US12/546,166 US7982638B2 (en) 2007-02-26 2009-08-24 Data transmission circuit and data communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053534 WO2008105053A1 (ja) 2007-02-26 2007-02-26 データ送信回路およびデータ送受信システム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/546,166 Continuation US7982638B2 (en) 2007-02-26 2009-08-24 Data transmission circuit and data communication system

Publications (1)

Publication Number Publication Date
WO2008105053A1 true WO2008105053A1 (ja) 2008-09-04

Family

ID=39720900

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053534 WO2008105053A1 (ja) 2007-02-26 2007-02-26 データ送信回路およびデータ送受信システム

Country Status (3)

Country Link
US (1) US7982638B2 (ja)
JP (1) JP4723029B2 (ja)
WO (1) WO2008105053A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011010220A (ja) * 2009-06-29 2011-01-13 Fujitsu Ltd データ送信回路
JP2016154904A (ja) * 2016-04-27 2016-09-01 株式会社藤商事 遊技機
JP2016174925A (ja) * 2016-04-27 2016-10-06 株式会社藤商事 遊技機

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7358872B2 (en) * 2005-09-01 2008-04-15 Micron Technology, Inc. Method and apparatus for converting parallel data to serial data in high speed applications
US7990296B1 (en) * 2010-03-10 2011-08-02 Smsc Holdings S.A.R.L. High speed low power cell providing serial differential signals
EP2515443A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA Data serializer
JP5807574B2 (ja) 2012-02-01 2015-11-10 富士通株式会社 送信回路、及び送信方法
JP6127807B2 (ja) 2013-07-26 2017-05-17 富士通株式会社 送信回路、通信システム及び通信方法
US9768809B2 (en) * 2014-06-30 2017-09-19 Intel IP Corporation Digital-to-time converter spur reduction
US11349481B1 (en) * 2021-02-19 2022-05-31 Skyechip Sdn Bhd I/O transmitter circuitry for supporting multi-modes serialization

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11215010A (ja) * 1998-01-23 1999-08-06 Fuji Film Microdevices Co Ltd パラレル−シリアル変換用差動論理回路
JP2001203585A (ja) * 2000-01-24 2001-07-27 Mitsubishi Electric Corp パラレル−シリアル変換回路
JP2002152053A (ja) * 2000-11-08 2002-05-24 Nec Microsystems Ltd パラレル−シリアル変換回路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6429122A (en) * 1987-07-24 1989-01-31 Omron Tateisi Electronics Co Parallel/serial converting circuit
US5012240A (en) * 1988-12-28 1991-04-30 Nippon Hoso Kyokai Parallel to serial converter with complementary bit insertion for disparity reduction
US5714904A (en) 1994-06-06 1998-02-03 Sun Microsystems, Inc. High speed serial link for fully duplexed data communication
JPH08328819A (ja) * 1995-06-02 1996-12-13 Sharp Corp 並列/直列データ変換装置
US6188339B1 (en) 1998-01-23 2001-02-13 Fuji Photo Film Co., Ltd. Differential multiplexer and differential logic circuit
US7101099B1 (en) * 1998-08-19 2006-09-05 Canon Kabushiki Kaisha Printing head, head cartridge having printing head, printing apparatus using printing head, and printing head substrate
JP2002175672A (ja) * 2000-12-05 2002-06-21 Fujitsu Ltd データ処理装置及びデータ処理方法
TWI242194B (en) 2001-09-26 2005-10-21 Sony Corp Parallel/serial conversion circuit, light output control circuit, and optical recording apparatus
JP4254492B2 (ja) 2003-11-07 2009-04-15 ソニー株式会社 データ伝送システム、データ送信装置、データ受信装置、データ伝送方法、データ送信方法及びデータ受信方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11215010A (ja) * 1998-01-23 1999-08-06 Fuji Film Microdevices Co Ltd パラレル−シリアル変換用差動論理回路
JP2001203585A (ja) * 2000-01-24 2001-07-27 Mitsubishi Electric Corp パラレル−シリアル変換回路
JP2002152053A (ja) * 2000-11-08 2002-05-24 Nec Microsystems Ltd パラレル−シリアル変換回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011010220A (ja) * 2009-06-29 2011-01-13 Fujitsu Ltd データ送信回路
JP2016154904A (ja) * 2016-04-27 2016-09-01 株式会社藤商事 遊技機
JP2016174925A (ja) * 2016-04-27 2016-10-06 株式会社藤商事 遊技機

Also Published As

Publication number Publication date
US7982638B2 (en) 2011-07-19
JP4723029B2 (ja) 2011-07-13
US20090309771A1 (en) 2009-12-17
JPWO2008105053A1 (ja) 2010-06-03

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