KR20080050461A - 고속 애플리케이션에서 병렬 데이터를 직렬 데이터로변환하기 위한 방법 및 장치 - Google Patents

고속 애플리케이션에서 병렬 데이터를 직렬 데이터로변환하기 위한 방법 및 장치 Download PDF

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Publication number
KR20080050461A
KR20080050461A KR1020087007861A KR20087007861A KR20080050461A KR 20080050461 A KR20080050461 A KR 20080050461A KR 1020087007861 A KR1020087007861 A KR 1020087007861A KR 20087007861 A KR20087007861 A KR 20087007861A KR 20080050461 A KR20080050461 A KR 20080050461A
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KR
South Korea
Prior art keywords
data
bit
buses
bus
alternately
Prior art date
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Withdrawn
Application number
KR1020087007861A
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English (en)
Korean (ko)
Inventor
크리스토퍼 케이. 모르자노
웬 리
Original Assignee
마이크론 테크놀로지, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 마이크론 테크놀로지, 인크. filed Critical 마이크론 테크놀로지, 인크.
Publication of KR20080050461A publication Critical patent/KR20080050461A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Bus Control (AREA)
  • Electronic Switches (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
KR1020087007861A 2005-09-01 2006-08-31 고속 애플리케이션에서 병렬 데이터를 직렬 데이터로변환하기 위한 방법 및 장치 Withdrawn KR20080050461A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/218,997 US7358872B2 (en) 2005-09-01 2005-09-01 Method and apparatus for converting parallel data to serial data in high speed applications
US11/218,997 2005-09-01

Publications (1)

Publication Number Publication Date
KR20080050461A true KR20080050461A (ko) 2008-06-05

Family

ID=37690564

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087007861A Withdrawn KR20080050461A (ko) 2005-09-01 2006-08-31 고속 애플리케이션에서 병렬 데이터를 직렬 데이터로변환하기 위한 방법 및 장치

Country Status (9)

Country Link
US (4) US7358872B2 (enExample)
EP (2) EP2287848A1 (enExample)
JP (1) JP2009507431A (enExample)
KR (1) KR20080050461A (enExample)
CN (1) CN101258555A (enExample)
AT (1) ATE491206T1 (enExample)
DE (1) DE602006018764D1 (enExample)
TW (1) TW200723713A (enExample)
WO (1) WO2007028095A2 (enExample)

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US8243543B2 (en) * 2008-02-29 2012-08-14 Hynix Semiconductor Inc. Semiconductor memory device for high-speed data input/output
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KR100948069B1 (ko) * 2008-09-10 2010-03-16 주식회사 하이닉스반도체 데이터 출력 회로
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KR101027681B1 (ko) * 2009-06-09 2011-04-12 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 정렬 회로
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
US8217814B1 (en) * 2010-12-17 2012-07-10 Mosys, Inc. Low power serial to parallel converter
CN102315852B (zh) * 2011-05-03 2014-07-30 四川和芯微电子股份有限公司 并串数据转换电路及并串数据转换系统
JP2012257047A (ja) * 2011-06-08 2012-12-27 Fujitsu Ltd パラレルシリアル変換回路、情報処理装置及び情報処理システム
US9098694B1 (en) * 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic
US8767463B2 (en) * 2011-08-11 2014-07-01 Smart Modular Technologies, Inc. Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof
US9530461B2 (en) * 2012-06-29 2016-12-27 Intel Corporation Architectures and techniques for providing low-power storage mechanisms
US8823558B2 (en) 2012-08-30 2014-09-02 International Business Machines Corporation Disparity reduction for high speed serial links
JP2014049173A (ja) * 2012-09-04 2014-03-17 Toshiba Corp 半導体記憶装置
US9405538B2 (en) * 2012-12-28 2016-08-02 Intel Corporation Functional unit having tree structure to support vector sorting algorithm and other algorithms
US9448965B2 (en) 2013-03-15 2016-09-20 Micron Technology, Inc. Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
CN104881390B (zh) * 2015-05-11 2018-02-27 杭州紫来测控技术有限公司 通过串行并行总线相互转换以减少线缆数量的方法
CN106095574B (zh) * 2016-06-13 2019-01-08 北京唯智佳辰科技发展有限责任公司 海量计算粗颗粒并行实现及计算任务随机动态分配方法
US10658041B1 (en) * 2018-11-30 2020-05-19 Micron Technology, Inc. Apparatus and methods for serializing data output
US11789835B2 (en) * 2020-11-20 2023-10-17 Micron Technology, Inc. Test input/output speed conversion and related apparatuses and methods
MY205100A (en) * 2020-12-29 2024-10-02 Skyechip Sdn Bhd A generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

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Also Published As

Publication number Publication date
US20070046511A1 (en) 2007-03-01
US7358872B2 (en) 2008-04-15
WO2007028095A2 (en) 2007-03-08
TW200723713A (en) 2007-06-16
US20080136690A1 (en) 2008-06-12
JP2009507431A (ja) 2009-02-19
EP1938329B1 (en) 2010-12-08
US7525458B2 (en) 2009-04-28
CN101258555A (zh) 2008-09-03
EP2287848A1 (en) 2011-02-23
US20090201746A1 (en) 2009-08-13
WO2007028095A3 (en) 2007-06-14
EP1938329A2 (en) 2008-07-02
DE602006018764D1 (de) 2011-01-20
US7764206B2 (en) 2010-07-27
US20100289678A1 (en) 2010-11-18
ATE491206T1 (de) 2010-12-15

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Date Code Title Description
PA0105 International application

Patent event date: 20080331

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid