JP2008537359A5 - - Google Patents

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Publication number
JP2008537359A5
JP2008537359A5 JP2008507794A JP2008507794A JP2008537359A5 JP 2008537359 A5 JP2008537359 A5 JP 2008537359A5 JP 2008507794 A JP2008507794 A JP 2008507794A JP 2008507794 A JP2008507794 A JP 2008507794A JP 2008537359 A5 JP2008537359 A5 JP 2008537359A5
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JP
Japan
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metal
work function
layer
cmos structure
cmos
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JP2008507794A
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English (en)
Japanese (ja)
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JP2008537359A (ja
JP5089576B2 (ja
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Priority claimed from US11/111,592 external-priority patent/US7598545B2/en
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Publication of JP2008537359A5 publication Critical patent/JP2008537359A5/ja
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Publication of JP5089576B2 publication Critical patent/JP5089576B2/ja
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JP2008507794A 2005-04-21 2006-04-18 自己整合され積極的にスケーリングされたｃｍｏｓデバイスにおけるゲート電極の金属／金属窒化物二重層のｃｍｏｓ構造体及び半導体構造体 Expired - Lifetime JP5089576B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/111,592 US7598545B2 (en) 2005-04-21 2005-04-21 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
US11/111,592 2005-04-21
PCT/US2006/014516 WO2006115894A2 (en) 2005-04-21 2006-04-18 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices

Publications (3)

Publication Number Publication Date
JP2008537359A JP2008537359A (ja) 2008-09-11
JP2008537359A5 true JP2008537359A5 (enExample) 2009-02-19
JP5089576B2 JP5089576B2 (ja) 2012-12-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008507794A Expired - Lifetime JP5089576B2 (ja) 2005-04-21 2006-04-18 自己整合され積極的にスケーリングされたｃｍｏｓデバイスにおけるゲート電極の金属／金属窒化物二重層のｃｍｏｓ構造体及び半導体構造体

Country Status (6)

Country Link
US (2) US7598545B2 (enExample)
EP (1) EP1872407B1 (enExample)
JP (1) JP5089576B2 (enExample)
CN (1) CN101421839B (enExample)
TW (1) TWI378558B (enExample)
WO (1) WO2006115894A2 (enExample)

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