JP2007513489A - 減少されたゲート高さを有するトランジスタを製造する方法 - Google Patents
減少されたゲート高さを有するトランジスタを製造する方法 Download PDFInfo
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Abstract
【解決手段】本方法は、基板、基板の上のゲート導体(13)、およびゲート導体(13)の上の少なくとも1つの犠牲層(14〜16)を有する積層構造を形成する。このプロセスは、積層構造を基板から延びる少なくとも1つのゲート・スタックにパターン形成し、ゲート・スタックに隣接してスペーサ(60)を形成し、ゲート・スタックに隣接してソースおよびドレイン領域(71)を形成するようにスペーサで保護されていない基板の領域にドーピングし、そして、スペーサ(60)および犠牲層(14〜16)を除去する。
【選択図】図30
Description
Claims (12)
- 減少されたゲート高さを有する集積回路トランジスタを形成する方法であって、
基板、前記基板の上のゲート導体(13)、および前記ゲート導体(13)の上の少なくとも1つの犠牲層(14〜16)を有する積層構造を形成するステップと、
前記積層構造を前記基板から延びる少なくとも1つのゲート・スタックにパターン形成するステップと、
前記ゲート・スタックに隣接してスペーサ(60)を形成するステップと、
前記ゲート・スタックに隣接してソースおよびドレイン領域(71)を形成するように、前記スペーサ(60)で保護されていない前記基板の領域にドーピングするステップと、
前記スペーサ(60)および前記犠牲層(14〜16)を除去するステップとを備える方法。 - 前記ゲート導体(13)の高さが、前記スペーサ(60)でつくられた前記ソースおよびドレイン領域(71)の間隔に関連したゲート高さよりも小さい、請求項1に記載の方法。
- 前記スペーサ(60)の寸法が、前記ゲート導体(13)と前記犠牲層(14〜16)との組み合わされた高さによって制御され、その結果、前記スペーサ(60)は、前記組み合わされた高さのために、前記ゲート導体(13)だけの高さに比べてより大きな間隔を実現するようになる、請求項1に記載の方法。
- 前記より大きな間隔は、前記ゲート導体(13)の前記高さだけに合わせて形成されるスペーサで形成されるソースおよびドレイン領域に比べて、前記ソースおよびドレイン領域(71)を前記ゲート導体(13)からより遠くに位置付けする、請求項3に記載の方法。
- 前記ゲート導体(13)の上の前記犠牲層(14〜16)が、
前記ゲート導体(13)の上に犠牲酸化物層(14)を形成するステップと、
前記酸化物層(14)の上に追加の犠牲層(15〜16)を形成するステップとを備えるプロセスで形成される、請求項1に記載の方法。 - 前記積層構造が前記ゲート導体(13)の下にシリコン層(11)を含み、そして、前記方法が、前記パターン形成するステップの後で、ソース/ドレイン電極(71)および前記ゲート導体(13)に一緒に自己整合打込みでドーピングするステップをさらに備え、
前記ゲート導体(13)と前記犠牲層(14〜16)との組み合わされた高さは、不純物が前記シリコン層(11)に達するのを妨げるが、
前記犠牲層(14〜16)がなければ、前記ドーピングするステップは前記ゲート導体(13)およびゲート誘電体層(12)を通して前記シリコン層(11)に不純物を打ち込む、請求項1に記載の方法。 - 前記積層構造が前記ゲート導体(13)の下にシリコン層(11)を含み、そして、前記方法が、
前記パターン形成するステップの後で、ソース/ドレイン電極(71)および前記ゲート導体(13)に一緒に自己整合打込みでドーピングする第1のドーピング・プロセスと、
前記第1のドーピング・プロセスの後で、前記第1のドーピング・プロセスで使用されたものと反対極性の不純物を、前記ゲート導体の下のハロー領域(102、106)に自己整合打込みでドーピングする第2のドーピング・プロセスとをさらに備え、
前記ゲート導体(13)と前記犠牲層(14〜16)との組み合わされた高さは、不純物が前記シリコン層(11)に達するのを妨げるが、
前記犠牲層(14〜16)がなければ、前記ドーピング・プロセスは前記ゲート導体(13)およびゲート誘電体層(12)を通して前記シリコン層(11)に不純物を打ち込む、請求項1に記載の方法。 - 前記スペーサ(60)が形成された後で、
前記ゲート・スタック(13)に隣接した前記基板上に隆起ソースおよびドレイン領域(71)をエピタキシャル成長するステップと、
前記隆起ソースおよびドレイン領域(71)ならびに前記基板に不純物を打ち込む(72)ステップとをさらに備える、請求項1に記載の方法。 - 積層スタック堆積を形成するステップであって、前記積層スタック堆積が、
基板層を覆ってシリコン層(11)を形成すること、
前記シリコン層(11)上にゲート酸化物(12)を形成すること、
前記ゲート酸化物(12)上にゲート導体(13)を形成すること、および、
前記ゲート導体(13)の上に少なくとも1つの犠牲層(14〜16)を形成することを備えるプロセスで形成されるステップと、
前記ゲート酸化物(12)、ゲート導体(13)、および前記犠牲層(14〜16)を少なくとも1つのゲート・スタックにパターン形成するステップと、
前記ゲート・スタックに隣接して一時的なスペーサ(60)を形成するステップと、
前記一時的なスペーサ(60)が隆起ソースおよびドレイン領域(71)を前記ゲート・スタックから分離させるような具合に、前記一時的なスペーサ(60)に隣接して前記基板層の上に前記隆起ソースおよびドレイン領域(71)をエピタキシャル成長するステップと、
前記隆起ソースおよびドレイン領域(71)上に追加の誘電体層(80)を成長するステップと、
前記犠牲層(14〜16)を除去することなしに、前記一時的なスペーサ(60)を除去するステップと、
前記隆起ソースおよびドレイン領域(71)、ならびに前記シリコン層(11)の露出領域にハロー打込み(100、104)を行うステップと、
前記ゲート・スタックに隣接して永久スペーサ(110)を形成するステップであって、前記永久スペーサ(110)が前記一時的なスペーサ(60)よりも薄いものであるステップと、
前記隆起ソースおよびドレイン領域(71)、ならびに前記シリコン層(11)の露出領域に不純物を打ち込む(112、114)ステップと、
前記永久スペーサ(110)と前記隆起ソースおよびドレイン領域(71)との間の前記シリコン(11)の前記露出領域を満たす最終スペーサ(120)を形成するステップと、
前記隆起ソースおよびドレイン領域(71)、ならびに前記シリコン(11)の露出領域に追加の不純物を打ち込むステップと、
すべての不純物を活性化するようにアニールするステップと、
前記隆起ソースおよびドレイン領域(71)上の前記追加の誘電体層(80)をエッチ・バックするステップと、
前記ゲート導体(13)と前記隆起ソースおよびドレイン領域(71)との両方をサリサイド化するステップとを備える、集積回路トランジスタを製造する方法。 - 前記隆起ソースおよびドレイン領域(71)をエピタキシャル成長する前記プロセスが、不純物をドーピングすることなしに行われる、請求項9に記載の方法。
- 前記犠牲層(14〜16)の前記除去が、前記スペーサ(60)でつくられた前記ソースおよびドレイン領域(71)の間隔に関連したゲート高さに比べて、前記ゲート導体(13)の高さを減少させる、請求項9に記載の方法。
- 前記ゲート導体(13)の上の前記犠牲層(14〜16)の前記形成が、前記ゲート導体(13)の上に犠牲酸化物層(14)を形成すること、前記酸化物層(14)の上に犠牲窒化物層(15)を形成すること、および前記窒化物層(15)の上に堅い犠牲絶縁物材料(16)を形成することをさらに備える、請求項9に記載の方法。
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US10/604,912 US20050048732A1 (en) | 2003-08-26 | 2003-08-26 | Method to produce transistor having reduced gate height |
PCT/US2004/020850 WO2005024899A2 (en) | 2003-08-26 | 2004-06-29 | Method to produce transistor having reduced gate height |
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JP (1) | JP2007513489A (ja) |
KR (1) | KR100861681B1 (ja) |
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WO2005024899A2 (en) | 2005-03-17 |
KR20060090217A (ko) | 2006-08-10 |
CN101405858A (zh) | 2009-04-08 |
EP1665334A4 (en) | 2011-02-23 |
WO2005024899A3 (en) | 2008-11-20 |
US20050048732A1 (en) | 2005-03-03 |
KR100861681B1 (ko) | 2008-10-07 |
EP1665334A2 (en) | 2006-06-07 |
CN101405858B (zh) | 2010-08-25 |
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