US7943467B2 - Structure and method to fabricate MOSFET with short gate - Google Patents
Structure and method to fabricate MOSFET with short gate Download PDFInfo
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- US7943467B2 US7943467B2 US12/016,317 US1631708A US7943467B2 US 7943467 B2 US7943467 B2 US 7943467B2 US 1631708 A US1631708 A US 1631708A US 7943467 B2 US7943467 B2 US 7943467B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions
- CMOS complementary metal oxide semiconductor
- a semiconducting device including a gate structure atop a substrate, the gate structure comprising a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor is composed of a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and forming a metal semiconductor alloy from the metal and the lower gate conductor.
- the metal that is deposited on the exposed lower gate conductor may be composed of Ni, Co, Ti, or Pt.
- the silicide formed from the deposited metal includes NiSi, NiSi 2 , NiPtSi, TiSi 2 , CoSi 2 , MoSi 2 , PtSi 2 , TaSi 2 , or WSi.
- producing the metal semiconductor alloy from the metal and the lower gate conductor includes an annealing step. In one embodiment when the polysilicon lower gate conductor is converted to NiSi 2 , the annealing step includes applying a temperature of approximately 300° C. to approximately 500° C. for a time period ranging from about 1 seconds to about 30 seconds.
- a method for producing a semiconducting device having a metal gate includes:
- a semiconducting device including a substrate, a dual gate conductor atop the substrate, and dopant regions in the substrate substantially corresponding (e.g., self aligned) to sidewalls of the dual gate conductor, the dual gate conductor including an upper gate conductor and a lower gate conductor, wherein the lower gate conductor is a metal gate; forming a contact metal layer on at least the dopant regions; removing the upper gate conductor; and producing a metal semiconductor alloy from the contact metal layer and the dopant regions.
- the dual gate conductor that is provided in the initial process steps of the present invention further includes a dielectric layer positioned between the upper gate conductor and the lower gate conductor and a gate dielectric positioned between the lower gate conductor and the substrate.
- the dielectric layer is composed of an oxide.
- removing the upper gate conductor further includes forming a contact metal layer on the upper surface of the semiconducting device, forming a metal nitride layer on the contact metal layer, removing at least the portion of the metal nitride layer and contact metal layer that are overlying the gate structure, as well as a portion of the upper gate conductor, and removing the remaining portion of the upper gate conductor to expose the dielectric layer.
- the substantially non-selective and substantially anisotropic material removal process includes ion milling.
- the step of removing the remaining portion of the upper gate conductor to expose the dielectric layer includes an etch process that removes the remaining portion of the upper gate conductor selective to the dielectric layer.
- a substrate including a channel positioned between a source region and a drain region
- a gate structure including a gate stack and at least one facetted spacer abutting the gate stack, the gate stack comprised of a gate dielectric positioned atop the channel of the substrate, and a gate conductor atop the gate dielectric, wherein the height of the at least one facetted spacer is greater than the height of the gate conductor.
- FIG. 4 is a side cross sectional view depicting one embodiment of depositing a second metal layer atop the structure depicted in FIG. 3 , in accordance with the present invention.
- the embodiments of the present invention relate to novel methods and structures relating to gate structures in semiconducting devices.
- inventive methods and structures relate to novel methods and structures relating to gate structures in semiconducting devices.
- P-type semiconductor refers to the addition of trivalent impurities to an intrinsic semiconductor that creates deficiencies of valence electrons, such as the addition of boron, aluminum, or gallium to a type IV semiconductor, such as Si.
- dual gate conductor denotes a gate region to a semiconducting device, such as a field effect transistor, that includes two gate conductors.
- gate conductor denotes a material having a conductivity ranging from 0.1 ⁇ /square to 20 ⁇ /square, which is positioned overlying a gate dielectric.
- a “metal” is an electrically conductive material, which in the metal atoms are held together by the force of a metallic bond, and the energy band structure of the metal's conduction and valence bands overlap, and hence, there is no energy gap.
- high K denotes a dielectric material featuring a dielectric constant (k) higher than about 3.9.
- references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- the first metal layer 16 may be composed of Ni, Co, Ti, Pt or combinations and alloys thereof at well as multilayers thereof. In one embodiment, the first metal layer 16 may have a thickness ranging from about 5 nm to about 20 nm. In another embodiment, the first metal layer 16 may have a thickness ranging from about 8 nm to about 15 nm.
- the metal nitride layer 17 may have a thickness ranging from about 3 nm to about 15 nm. In another embodiment, the metal nitride layer 17 may have a thickness ranging from about 4 nm to about 7 nm.
- the deposition method of metal nitride layer includes chemical vapor deposition (CVD). In one embodiment, the metal nitride layer 17 is deposited by physical vapor deposition (PVD), which may include but is not limited to: plating, sputter deposition, molecular beam epitaxial deposition, electron beam deposition and combinations thereof.
- PVD physical vapor deposition
- the angle of incidence of ions impinging on the upper surface of the at least one dielectric spacer 20 is selected to provide an etched spacer 20 a having a facetted upper surface 21 , which is hereafter referred to as a facetted spacer 20 a .
- the facetted upper surface 21 is a planar surface, wherein the facet angle ⁇ at the intersection of the planar surface 21 to the sidewall 22 of the facetted spacer 20 a that is abutting the gate stack 111 is at an acute angle.
- the facet angle ⁇ is less than 75°.
- the facet angle ⁇ ranges from about 20 degrees to about 60 degrees.
- the facet angle ⁇ ranges from about 25 degrees to about 45 degrees.
- the facet angle ⁇ is less than 30°.
- FIG. 4 depicts removing the upper gate conductor 12 selective to the lower gate conductor 14 and depositing a metal (hereafter referred to as a second metal layer 18 ) on the lower gate conductor 12 , in accordance with one embodiment of the present invention.
- removing the upper gate conductor 12 selective to the lower gate conductor 14 includes removing a portion of the upper gate conductor 12 that remains following the above described ion milling step with an etch process selective to the underlying sacrificial dielectric layer 13 . Thereafter, the sacrificial dielectric layer 13 is removed by an etch process selective to the lower gate conductor 14 , hence exposing the upper surface of the lower gate conductor 14 .
- FIG. 6 depicts one embodiment of an etch process to remove un-reacted metals following the alloying of the second metal layer 18 with the lower gate conductor 14 and the source/drain regions 7 .
- the etch process includes a wet etch that removes the unreacted portions of the first metal layer 16 , the metal nitride layer 17 , and the second metal layer 18 selective to the substrate 5 , the facetted spacer 20 a , and the silicide gate 100 .
- the gate dielectric 15 includes a high k dielectric comprised of an oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- the lower gate conductor 114 is composed of TiN and the gate dielectric 15 is composed of HfO 2 .
- the annealing step includes a temperature ranging from approximately 600° C. to approximately 700° C. for a time period ranging from approximately 1 second to approximately 30 seconds to provide cobalt silicide (CoSi 2 ) contacts 105 .
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Abstract
Description
removing the upper gate conductor selective to the lower gate conductor;
depositing a metal on at least the lower gate conductor; and
forming a metal semiconductor alloy from the metal and the lower gate conductor.
forming a contact metal layer on at least the dopant regions;
removing the upper gate conductor; and
producing a metal semiconductor alloy from the contact metal layer and the dopant regions.
Claims (15)
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US12/016,317 US7943467B2 (en) | 2008-01-18 | 2008-01-18 | Structure and method to fabricate MOSFET with short gate |
CN200910004832XA CN101488453B (en) | 2008-01-18 | 2009-01-19 | Structure and method to fabricate MOSFET with short gate |
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US8779514B2 (en) | 2010-12-29 | 2014-07-15 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor and method for manufacturing the same |
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CN102339752A (en) * | 2010-07-14 | 2012-02-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device based on gate replacement process |
CN102569396B (en) * | 2010-12-29 | 2015-09-23 | 中国科学院微电子研究所 | Transistor and method of manufacturing the same |
US8673758B2 (en) * | 2011-06-16 | 2014-03-18 | United Microelectronics Corp. | Structure of metal gate and fabrication method thereof |
US9443957B1 (en) | 2015-03-12 | 2016-09-13 | International Business Machines Corporation | Self-aligned source and drain regions for semiconductor devices |
US9691871B1 (en) * | 2015-12-18 | 2017-06-27 | Stmicroelectronics (Crolles 2) Sas | Process for forming a layer of equiaxed titanium nitride and a MOSFET device having a metal gate electrode including a layer of equiaxed titanium nitride |
US20190259618A1 (en) * | 2018-02-19 | 2019-08-22 | Stmicroelectronics (Crolles 2) Sas | Process for forming a layer of a work function metal for a mosfet gate having a uniaxial grain orientation |
US10840133B2 (en) | 2018-09-27 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with staggered selective growth |
DE102019109846A1 (en) * | 2018-09-27 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR STRUCTURE WITH STAGE SELECTIVE GROWTH |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050048732A1 (en) | 2003-08-26 | 2005-03-03 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
US20050191833A1 (en) * | 2004-02-27 | 2005-09-01 | Samsung Electronics Co., Ltd. | Method of fabricating MOS transistor having fully silicided gate |
CN1294648C (en) | 2002-11-20 | 2007-01-10 | 国际商业机器公司 | Method and process to make multiple-threshold value |
CN101159232A (en) | 2006-10-05 | 2008-04-09 | 台湾积体电路制造股份有限公司 | Method of making fusi gate and resulting structure |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1294648C (en) | 2002-11-20 | 2007-01-10 | 国际商业机器公司 | Method and process to make multiple-threshold value |
US20050048732A1 (en) | 2003-08-26 | 2005-03-03 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
US20050191833A1 (en) * | 2004-02-27 | 2005-09-01 | Samsung Electronics Co., Ltd. | Method of fabricating MOS transistor having fully silicided gate |
CN101159232A (en) | 2006-10-05 | 2008-04-09 | 台湾积体电路制造股份有限公司 | Method of making fusi gate and resulting structure |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779514B2 (en) | 2010-12-29 | 2014-07-15 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor and method for manufacturing the same |
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