JP2007195168A - オンダイターミネーション制御装置 - Google Patents

オンダイターミネーション制御装置 Download PDF

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Publication number
JP2007195168A
JP2007195168A JP2006355185A JP2006355185A JP2007195168A JP 2007195168 A JP2007195168 A JP 2007195168A JP 2006355185 A JP2006355185 A JP 2006355185A JP 2006355185 A JP2006355185 A JP 2006355185A JP 2007195168 A JP2007195168 A JP 2007195168A
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JP
Japan
Prior art keywords
die termination
pulse signal
termination control
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006355185A
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English (en)
Japanese (ja)
Other versions
JP2007195168A5 (https=
Inventor
Dong Uk Lee
東 郁 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2007195168A publication Critical patent/JP2007195168A/ja
Publication of JP2007195168A5 publication Critical patent/JP2007195168A5/ja
Pending legal-status Critical Current

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Classifications

    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47C—CHAIRS; SOFAS; BEDS
    • A47C31/00—Details or accessories for chairs, beds, or the like, not provided for in other groups of this subclass, e.g. upholstery fasteners, mattress protectors, stretching devices for mattress nets
    • A47C31/10—Loose or removable furniture covers
    • A47C31/105—Loose or removable furniture covers for mattresses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47G—HOUSEHOLD OR TABLE EQUIPMENT
    • A47G9/00—Bed-covers; Counterpanes; Travelling rugs; Sleeping rugs; Sleeping bags; Pillows
    • A47G9/02—Bed linen; Blankets; Counterpanes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0298—Arrangement for terminating transmission lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
JP2006355185A 2006-01-16 2006-12-28 オンダイターミネーション制御装置 Pending JP2007195168A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060004366A KR100681879B1 (ko) 2006-01-16 2006-01-16 온-다이 터미네이션 제어 장치

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012228374A Division JP2013048459A (ja) 2006-01-16 2012-10-15 オンダイターミネーション制御装置

Publications (2)

Publication Number Publication Date
JP2007195168A true JP2007195168A (ja) 2007-08-02
JP2007195168A5 JP2007195168A5 (https=) 2010-02-04

Family

ID=38106212

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2006355185A Pending JP2007195168A (ja) 2006-01-16 2006-12-28 オンダイターミネーション制御装置
JP2012228374A Pending JP2013048459A (ja) 2006-01-16 2012-10-15 オンダイターミネーション制御装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012228374A Pending JP2013048459A (ja) 2006-01-16 2012-10-15 オンダイターミネーション制御装置

Country Status (5)

Country Link
US (2) US7288959B1 (https=)
JP (2) JP2007195168A (https=)
KR (1) KR100681879B1 (https=)
CN (1) CN101025995B (https=)
TW (1) TWI336559B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014230091A (ja) * 2013-05-22 2014-12-08 富士通株式会社 抵抗調整回路、及び、抵抗調整方法

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KR100674978B1 (ko) * 2005-06-27 2007-01-29 삼성전자주식회사 반도체 장치의 일부 어드레스 핀의 터미네이션 값을조절하는 방법 및 이를 이용한 반도체 장치
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치
KR100780949B1 (ko) * 2006-03-21 2007-12-03 삼성전자주식회사 데이터 독출 모드에서 ｏｄｔ 회로의 온/오프 상태를테스트할 수 있는 반도체 메모리 장치 및 ｏｄｔ 회로의상태 테스트 방법
US7692446B2 (en) 2006-08-24 2010-04-06 Hynix Semiconductor, Inc. On-die termination device
KR100838366B1 (ko) 2007-04-02 2008-06-13 주식회사 하이닉스반도체 오프셋 보상이 가능한 온 다이 터미네이션 장치의캘리브래이션 회로.
KR100866927B1 (ko) * 2006-09-27 2008-11-04 주식회사 하이닉스반도체 온 다이 터미네이션 회로 및 그의 구동방법
US7372295B1 (en) * 2006-12-22 2008-05-13 Altera Corporation Techniques for calibrating on-chip termination impedances
KR100834933B1 (ko) 2007-03-30 2008-06-03 경상대학교산학협력단 비교기의 옵셋을 줄이기 위한 방법 및 그 장치
US20080246537A1 (en) * 2007-04-03 2008-10-09 Broadcom Corporation Programmable discontinuity resistors for reference ladders
JP4920512B2 (ja) 2007-07-04 2012-04-18 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、データ処理システム
US7817467B2 (en) * 2007-09-07 2010-10-19 Micron Technology, Inc. Memory controller self-calibration for removing systemic influence
KR100897293B1 (ko) * 2007-11-12 2009-05-14 주식회사 하이닉스반도체 반도체 장치, 반도체 장치의 온 다이 터미네이션 회로 및그 제어 방법
KR100897302B1 (ko) * 2008-04-10 2009-05-14 주식회사 하이닉스반도체 데이터 라인 터미네이션 회로
JP5157607B2 (ja) * 2008-04-11 2013-03-06 日本電気株式会社 半導体装置及び半導体装置のインピーダンス調整方法
KR100899570B1 (ko) * 2008-04-21 2009-05-27 주식회사 하이닉스반도체 온 다이 터미네이션 장치의 캘리브래이션 회로
FR2932904B1 (fr) * 2008-06-19 2011-02-25 Eads Europ Aeronautic Defence Procede de detection de correction d'erreurs pour une memoire dont la structure est a comportement dissymetrique
KR100980414B1 (ko) 2008-11-12 2010-09-07 주식회사 하이닉스반도체 캘리브레이션 회로 및 이를 이용하는 데이터 출력 회로
JP2010219751A (ja) 2009-03-16 2010-09-30 Elpida Memory Inc 半導体装置
KR101094984B1 (ko) * 2010-03-31 2011-12-20 주식회사 하이닉스반도체 반도체 집적회로의 임피던스 조정 장치
KR101113329B1 (ko) * 2010-04-01 2012-02-24 주식회사 하이닉스반도체 온다이 터미네이션 회로
KR20130032702A (ko) 2011-09-23 2013-04-02 에스케이하이닉스 주식회사 비교회로 및 이를 이용한 임피던스 교정회로.
KR20130093231A (ko) * 2012-02-14 2013-08-22 에스케이하이닉스 주식회사 저항 측정 회로, 저항 측정 방법 그리고 임피던스 조절회로
US9571098B2 (en) 2014-08-11 2017-02-14 Samsung Electronics Co., Ltd. Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
US10679909B2 (en) * 2016-11-21 2020-06-09 Kla-Tencor Corporation System, method and non-transitory computer readable medium for tuning sensitivies of, and determining a process window for, a modulated wafer
CN108206037B (zh) * 2016-12-16 2021-01-15 晶豪科技股份有限公司 在存储器装置的zq校准中决定电阻校准方向的方法
KR20190075788A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 캘리브레이션 장치를 포함하는 스토리지 장치
EP3731411A4 (en) * 2019-01-18 2021-01-13 Shenzhen Goodix Technology Co., Ltd. SIGNAL GENERATION CIRCUIT, ASSOCIATED CHIP, FLOW METER AND PROCEDURE
US10630289B1 (en) * 2019-03-01 2020-04-21 Realtek Semiconductor Corp. On-die-termination circuit and control method for of the same
CN116107384B (zh) * 2021-11-11 2025-09-23 瑞昱半导体股份有限公司 具有自参考阻抗的集成电路
CN114915284A (zh) * 2022-05-31 2022-08-16 上海金脉电子科技有限公司 开关控制电路、电机驱动系统及车辆
US12143084B1 (en) 2023-04-18 2024-11-12 Nanya Technology Corporation Impedance adjusting circuit and impedance adjusting method for zero quotient calibration

Citations (5)

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JPS60142610A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd コンパレ−タ回路
JPH06232706A (ja) * 1993-02-05 1994-08-19 Nec Corp 比較器
JP2002330182A (ja) * 2001-02-05 2002-11-15 Samsung Electronics Co Ltd ターミネーション回路のインピーダンスアップデート装置及び方法
JP2003345735A (ja) * 2002-05-24 2003-12-05 Samsung Electronics Co Ltd ターミネーション制御回路及びその方法
US20050242833A1 (en) * 2004-04-28 2005-11-03 Nak Kyu Park On-die termination impedance calibration device

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Publication number Priority date Publication date Assignee Title
JPS60142610A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd コンパレ−タ回路
JPH06232706A (ja) * 1993-02-05 1994-08-19 Nec Corp 比較器
JP2002330182A (ja) * 2001-02-05 2002-11-15 Samsung Electronics Co Ltd ターミネーション回路のインピーダンスアップデート装置及び方法
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014230091A (ja) * 2013-05-22 2014-12-08 富士通株式会社 抵抗調整回路、及び、抵抗調整方法

Also Published As

Publication number Publication date
US7288959B1 (en) 2007-10-30
US20070164780A1 (en) 2007-07-19
CN101025995A (zh) 2007-08-29
TW200731662A (en) 2007-08-16
TWI336559B (en) 2011-01-21
KR100681879B1 (ko) 2007-02-15
JP2013048459A (ja) 2013-03-07
US7888963B2 (en) 2011-02-15
US20080001624A1 (en) 2008-01-03
CN101025995B (zh) 2010-04-14

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