CN101025995B - 用于控制内建终端的装置 - Google Patents

用于控制内建终端的装置 Download PDF

Info

Publication number
CN101025995B
CN101025995B CN2006101683792A CN200610168379A CN101025995B CN 101025995 B CN101025995 B CN 101025995B CN 2006101683792 A CN2006101683792 A CN 2006101683792A CN 200610168379 A CN200610168379 A CN 200610168379A CN 101025995 B CN101025995 B CN 101025995B
Authority
CN
China
Prior art keywords
pulse signal
voltage
die termination
control unit
comparer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006101683792A
Other languages
English (en)
Chinese (zh)
Other versions
CN101025995A (zh
Inventor
李东郁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101025995A publication Critical patent/CN101025995A/zh
Application granted granted Critical
Publication of CN101025995B publication Critical patent/CN101025995B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47C—CHAIRS; SOFAS; BEDS
    • A47C31/00—Details or accessories for chairs, beds, or the like, not provided for in other groups of this subclass, e.g. upholstery fasteners, mattress protectors, stretching devices for mattress nets
    • A47C31/10—Loose or removable furniture covers
    • A47C31/105—Loose or removable furniture covers for mattresses
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47G—HOUSEHOLD OR TABLE EQUIPMENT
    • A47G9/00—Bed-covers; Counterpanes; Travelling rugs; Sleeping rugs; Sleeping bags; Pillows
    • A47G9/02—Bed linen; Blankets; Counterpanes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0298—Arrangement for terminating transmission lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
CN2006101683792A 2006-01-16 2006-12-27 用于控制内建终端的装置 Expired - Fee Related CN101025995B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020060004366A KR100681879B1 (ko) 2006-01-16 2006-01-16 온-다이 터미네이션 제어 장치
KR10-2006-0004366 2006-01-16
KR1020060004366 2006-01-16

Publications (2)

Publication Number Publication Date
CN101025995A CN101025995A (zh) 2007-08-29
CN101025995B true CN101025995B (zh) 2010-04-14

Family

ID=38106212

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006101683792A Expired - Fee Related CN101025995B (zh) 2006-01-16 2006-12-27 用于控制内建终端的装置

Country Status (5)

Country Link
US (2) US7288959B1 (https=)
JP (2) JP2007195168A (https=)
KR (1) KR100681879B1 (https=)
CN (1) CN101025995B (https=)
TW (1) TWI336559B (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674978B1 (ko) * 2005-06-27 2007-01-29 삼성전자주식회사 반도체 장치의 일부 어드레스 핀의 터미네이션 값을조절하는 방법 및 이를 이용한 반도체 장치
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치
KR100780949B1 (ko) * 2006-03-21 2007-12-03 삼성전자주식회사 데이터 독출 모드에서 ｏｄｔ 회로의 온/오프 상태를테스트할 수 있는 반도체 메모리 장치 및 ｏｄｔ 회로의상태 테스트 방법
US7692446B2 (en) 2006-08-24 2010-04-06 Hynix Semiconductor, Inc. On-die termination device
KR100838366B1 (ko) 2007-04-02 2008-06-13 주식회사 하이닉스반도체 오프셋 보상이 가능한 온 다이 터미네이션 장치의캘리브래이션 회로.
KR100866927B1 (ko) * 2006-09-27 2008-11-04 주식회사 하이닉스반도체 온 다이 터미네이션 회로 및 그의 구동방법
US7372295B1 (en) * 2006-12-22 2008-05-13 Altera Corporation Techniques for calibrating on-chip termination impedances
KR100834933B1 (ko) 2007-03-30 2008-06-03 경상대학교산학협력단 비교기의 옵셋을 줄이기 위한 방법 및 그 장치
US20080246537A1 (en) * 2007-04-03 2008-10-09 Broadcom Corporation Programmable discontinuity resistors for reference ladders
JP4920512B2 (ja) 2007-07-04 2012-04-18 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、データ処理システム
US7817467B2 (en) * 2007-09-07 2010-10-19 Micron Technology, Inc. Memory controller self-calibration for removing systemic influence
KR100897293B1 (ko) * 2007-11-12 2009-05-14 주식회사 하이닉스반도체 반도체 장치, 반도체 장치의 온 다이 터미네이션 회로 및그 제어 방법
KR100897302B1 (ko) * 2008-04-10 2009-05-14 주식회사 하이닉스반도체 데이터 라인 터미네이션 회로
JP5157607B2 (ja) * 2008-04-11 2013-03-06 日本電気株式会社 半導体装置及び半導体装置のインピーダンス調整方法
KR100899570B1 (ko) * 2008-04-21 2009-05-27 주식회사 하이닉스반도체 온 다이 터미네이션 장치의 캘리브래이션 회로
FR2932904B1 (fr) * 2008-06-19 2011-02-25 Eads Europ Aeronautic Defence Procede de detection de correction d'erreurs pour une memoire dont la structure est a comportement dissymetrique
KR100980414B1 (ko) 2008-11-12 2010-09-07 주식회사 하이닉스반도체 캘리브레이션 회로 및 이를 이용하는 데이터 출력 회로
JP2010219751A (ja) 2009-03-16 2010-09-30 Elpida Memory Inc 半導体装置
KR101094984B1 (ko) * 2010-03-31 2011-12-20 주식회사 하이닉스반도체 반도체 집적회로의 임피던스 조정 장치
KR101113329B1 (ko) * 2010-04-01 2012-02-24 주식회사 하이닉스반도체 온다이 터미네이션 회로
KR20130032702A (ko) 2011-09-23 2013-04-02 에스케이하이닉스 주식회사 비교회로 및 이를 이용한 임피던스 교정회로.
KR20130093231A (ko) * 2012-02-14 2013-08-22 에스케이하이닉스 주식회사 저항 측정 회로, 저항 측정 방법 그리고 임피던스 조절회로
JP6126458B2 (ja) * 2013-05-22 2017-05-10 富士通株式会社 抵抗調整回路、及び、抵抗調整方法
US9571098B2 (en) 2014-08-11 2017-02-14 Samsung Electronics Co., Ltd. Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
US10679909B2 (en) * 2016-11-21 2020-06-09 Kla-Tencor Corporation System, method and non-transitory computer readable medium for tuning sensitivies of, and determining a process window for, a modulated wafer
CN108206037B (zh) * 2016-12-16 2021-01-15 晶豪科技股份有限公司 在存储器装置的zq校准中决定电阻校准方向的方法
KR20190075788A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 캘리브레이션 장치를 포함하는 스토리지 장치
EP3731411A4 (en) * 2019-01-18 2021-01-13 Shenzhen Goodix Technology Co., Ltd. SIGNAL GENERATION CIRCUIT, ASSOCIATED CHIP, FLOW METER AND PROCEDURE
US10630289B1 (en) * 2019-03-01 2020-04-21 Realtek Semiconductor Corp. On-die-termination circuit and control method for of the same
CN116107384B (zh) * 2021-11-11 2025-09-23 瑞昱半导体股份有限公司 具有自参考阻抗的集成电路
CN114915284A (zh) * 2022-05-31 2022-08-16 上海金脉电子科技有限公司 开关控制电路、电机驱动系统及车辆
US12143084B1 (en) 2023-04-18 2024-11-12 Nanya Technology Corporation Impedance adjusting circuit and impedance adjusting method for zero quotient calibration

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1519853A (zh) * 2002-11-20 2004-08-11 ���ǵ�����ʽ���� 用于降低单片直流电流的片上终接电路、方法及存储系统
US6924660B2 (en) * 2003-09-08 2005-08-02 Rambus Inc. Calibration methods and circuits for optimized on-die termination
CN1655279A (zh) * 2004-02-13 2005-08-17 海力士半导体有限公司 在半导体存储器装置中的片内终结上的模式转移电路

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142610A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd コンパレ−タ回路
JPS6184110A (ja) * 1984-10-01 1986-04-28 Nec Corp 電圧比較器
JPS62269512A (ja) * 1986-05-19 1987-11-24 Nippon Telegr & Teleph Corp <Ntt> 電圧比較器
JPH06232706A (ja) * 1993-02-05 1994-08-19 Nec Corp 比較器
US6026456A (en) 1995-12-15 2000-02-15 Intel Corporation System utilizing distributed on-chip termination
JPH10261948A (ja) * 1997-03-17 1998-09-29 Nec Corp 出力インピーダンス自己補正回路付半導体集積回路
US6157206A (en) 1998-12-31 2000-12-05 Intel Corporation On-chip termination
KR100410536B1 (ko) * 2001-02-05 2003-12-18 삼성전자주식회사 터미네이션 회로의 임피던스 업데이트 장치 및 방법
ATE401694T1 (de) 2001-04-11 2008-08-15 Nxp Bv Offsetspannungskompensation mit hohem tastverhältnis für operationsverstärker
KR100403633B1 (ko) * 2001-08-10 2003-10-30 삼성전자주식회사 임피던스 제어회로
JP3702227B2 (ja) * 2002-01-09 2005-10-05 株式会社東芝 半導体装置
KR100468728B1 (ko) * 2002-04-19 2005-01-29 삼성전자주식회사 반도체 집적회로의 온-칩 터미네이터, 그 제어 회로 및 그제어 방법
KR100422451B1 (ko) * 2002-05-24 2004-03-11 삼성전자주식회사 온-다이 터미네이션 제어방법 및 그에 따른 제어회로
TW544995B (en) 2002-08-09 2003-08-01 Advanic Technologies Inc Flash A/D converter with new autozeroing and interpolation possessing negative impedance compensation
KR100532426B1 (ko) * 2003-03-25 2005-11-30 삼성전자주식회사 온-칩 터미네이션 저항의 미스매치를 보상할 수 있는반도체 장치
KR100502664B1 (ko) * 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
US7205787B1 (en) * 2003-11-24 2007-04-17 Neascape, Inc. On-chip termination for a high-speed single-ended interface
KR100515068B1 (ko) * 2003-12-19 2005-09-16 주식회사 하이닉스반도체 반도체 기억 소자의 온 다이 터미네이션을 위한 회로 및방법
KR100578649B1 (ko) * 2004-04-20 2006-05-11 주식회사 하이닉스반도체 온-다이 터미네이션 제어 회로 및 온-다이 터미네이션제어 신호 생성 방법
KR100532972B1 (ko) * 2004-04-28 2005-12-01 주식회사 하이닉스반도체 온 다이 터미네이션 임피던스 조절 장치
KR100670702B1 (ko) 2004-10-30 2007-01-17 주식회사 하이닉스반도체 온다이 터미네이션 회로를 구비한 반도체 메모리 장치
US7138823B2 (en) * 2005-01-20 2006-11-21 Micron Technology, Inc. Apparatus and method for independent control of on-die termination for output buffers of a memory device
US7218155B1 (en) * 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7221193B1 (en) * 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1519853A (zh) * 2002-11-20 2004-08-11 ���ǵ�����ʽ���� 用于降低单片直流电流的片上终接电路、方法及存储系统
US6924660B2 (en) * 2003-09-08 2005-08-02 Rambus Inc. Calibration methods and circuits for optimized on-die termination
CN1655279A (zh) * 2004-02-13 2005-08-17 海力士半导体有限公司 在半导体存储器装置中的片内终结上的模式转移电路

Also Published As

Publication number Publication date
JP2007195168A (ja) 2007-08-02
US7288959B1 (en) 2007-10-30
US20070164780A1 (en) 2007-07-19
CN101025995A (zh) 2007-08-29
TW200731662A (en) 2007-08-16
TWI336559B (en) 2011-01-21
KR100681879B1 (ko) 2007-02-15
JP2013048459A (ja) 2013-03-07
US7888963B2 (en) 2011-02-15
US20080001624A1 (en) 2008-01-03

Similar Documents

Publication Publication Date Title
CN101025995B (zh) 用于控制内建终端的装置
JP6140860B2 (ja) シングルエンド構成可能マルチモードドライバ
US7750666B2 (en) Reduced power differential type termination circuit
US8401098B2 (en) Digital differential signal transmitter for low supply voltage
US7135884B1 (en) Voltage mode transceiver having programmable voltage swing and external reference-based calibration
US7208973B2 (en) On die termination circuit
US8035418B2 (en) Output driver
CN110390966A (zh) 终结电路、半导体器件及其操作方法
US8810274B2 (en) On-die termination circuit
US20080136467A1 (en) Buffer chain driver
US7084662B1 (en) Variable impedance output driver
US7279937B2 (en) Programmable amplitude line driver
US12166485B2 (en) Methods and circuits for slew-rate calibration
US7888962B1 (en) Impedance matching circuit
US6825708B1 (en) Apparatus and method for an offset-correcting sense amplifier
EP1352472A1 (en) Circuit for receiving and driving a clock-signal
US7633318B2 (en) Data receiver of semiconductor integrated circuit and method for controlling the same
JP3805311B2 (ja) 出力回路
US8890583B2 (en) Data transmission circuits and system having the same
JP2005269336A (ja) 信号伝送回路、信号出力回路および信号伝送回路の終端方法
US7746096B1 (en) Impedance buffer and method
US9543904B1 (en) Differential amplifier circuit and semiconductor memory device including same
US20160329887A1 (en) Transmitting/receiving system
US12301187B2 (en) Signal input/output circuit and method of operating the signal input/output circuit
US7826275B2 (en) Memory circuit with high reading speed and low switching noise

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100414

Termination date: 20131227