TWI336559B - Apparatus for controlling on-die termination - Google Patents

Apparatus for controlling on-die termination Download PDF

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Publication number
TWI336559B
TWI336559B TW095146506A TW95146506A TWI336559B TW I336559 B TWI336559 B TW I336559B TW 095146506 A TW095146506 A TW 095146506A TW 95146506 A TW95146506 A TW 95146506A TW I336559 B TWI336559 B TW I336559B
Authority
TW
Taiwan
Prior art keywords
pulse signal
terminal
signal
wafer
voltage
Prior art date
Application number
TW095146506A
Other languages
English (en)
Chinese (zh)
Other versions
TW200731662A (en
Inventor
Dong-Uk Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200731662A publication Critical patent/TW200731662A/zh
Application granted granted Critical
Publication of TWI336559B publication Critical patent/TWI336559B/zh

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005Modifications of input or output impedance
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47CCHAIRS; SOFAS; BEDS
    • A47C31/00Details or accessories for chairs, beds, or the like, not provided for in other groups of this subclass, e.g. upholstery fasteners, mattress protectors, stretching devices for mattress nets
    • A47C31/10Loose or removable furniture covers
    • A47C31/105Loose or removable furniture covers for mattresses
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47GHOUSEHOLD OR TABLE EQUIPMENT
    • A47G9/00Bed-covers; Counterpanes; Travelling rugs; Sleeping rugs; Sleeping bags; Pillows
    • A47G9/02Bed linen; Blankets; Counterpanes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0298Arrangement for terminating transmission lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
TW095146506A 2006-01-16 2006-12-12 Apparatus for controlling on-die termination TWI336559B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060004366A KR100681879B1 (ko) 2006-01-16 2006-01-16 온-다이 터미네이션 제어 장치

Publications (2)

Publication Number Publication Date
TW200731662A TW200731662A (en) 2007-08-16
TWI336559B true TWI336559B (en) 2011-01-21

Family

ID=38106212

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095146506A TWI336559B (en) 2006-01-16 2006-12-12 Apparatus for controlling on-die termination

Country Status (5)

Country Link
US (2) US7288959B1 (https=)
JP (2) JP2007195168A (https=)
KR (1) KR100681879B1 (https=)
CN (1) CN101025995B (https=)
TW (1) TWI336559B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12143084B1 (en) 2023-04-18 2024-11-12 Nanya Technology Corporation Impedance adjusting circuit and impedance adjusting method for zero quotient calibration

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674978B1 (ko) * 2005-06-27 2007-01-29 삼성전자주식회사 반도체 장치의 일부 어드레스 핀의 터미네이션 값을조절하는 방법 및 이를 이용한 반도체 장치
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치
KR100780949B1 (ko) * 2006-03-21 2007-12-03 삼성전자주식회사 데이터 독출 모드에서 odt 회로의 온/오프 상태를테스트할 수 있는 반도체 메모리 장치 및 odt 회로의상태 테스트 방법
US7692446B2 (en) 2006-08-24 2010-04-06 Hynix Semiconductor, Inc. On-die termination device
KR100838366B1 (ko) 2007-04-02 2008-06-13 주식회사 하이닉스반도체 오프셋 보상이 가능한 온 다이 터미네이션 장치의캘리브래이션 회로.
KR100866927B1 (ko) * 2006-09-27 2008-11-04 주식회사 하이닉스반도체 온 다이 터미네이션 회로 및 그의 구동방법
US7372295B1 (en) * 2006-12-22 2008-05-13 Altera Corporation Techniques for calibrating on-chip termination impedances
KR100834933B1 (ko) 2007-03-30 2008-06-03 경상대학교산학협력단 비교기의 옵셋을 줄이기 위한 방법 및 그 장치
US20080246537A1 (en) * 2007-04-03 2008-10-09 Broadcom Corporation Programmable discontinuity resistors for reference ladders
JP4920512B2 (ja) 2007-07-04 2012-04-18 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、データ処理システム
US7817467B2 (en) * 2007-09-07 2010-10-19 Micron Technology, Inc. Memory controller self-calibration for removing systemic influence
KR100897293B1 (ko) * 2007-11-12 2009-05-14 주식회사 하이닉스반도체 반도체 장치, 반도체 장치의 온 다이 터미네이션 회로 및그 제어 방법
KR100897302B1 (ko) * 2008-04-10 2009-05-14 주식회사 하이닉스반도체 데이터 라인 터미네이션 회로
JP5157607B2 (ja) * 2008-04-11 2013-03-06 日本電気株式会社 半導体装置及び半導体装置のインピーダンス調整方法
KR100899570B1 (ko) * 2008-04-21 2009-05-27 주식회사 하이닉스반도체 온 다이 터미네이션 장치의 캘리브래이션 회로
FR2932904B1 (fr) * 2008-06-19 2011-02-25 Eads Europ Aeronautic Defence Procede de detection de correction d'erreurs pour une memoire dont la structure est a comportement dissymetrique
KR100980414B1 (ko) 2008-11-12 2010-09-07 주식회사 하이닉스반도체 캘리브레이션 회로 및 이를 이용하는 데이터 출력 회로
JP2010219751A (ja) 2009-03-16 2010-09-30 Elpida Memory Inc 半導体装置
KR101094984B1 (ko) * 2010-03-31 2011-12-20 주식회사 하이닉스반도체 반도체 집적회로의 임피던스 조정 장치
KR101113329B1 (ko) * 2010-04-01 2012-02-24 주식회사 하이닉스반도체 온다이 터미네이션 회로
KR20130032702A (ko) 2011-09-23 2013-04-02 에스케이하이닉스 주식회사 비교회로 및 이를 이용한 임피던스 교정회로.
KR20130093231A (ko) * 2012-02-14 2013-08-22 에스케이하이닉스 주식회사 저항 측정 회로, 저항 측정 방법 그리고 임피던스 조절회로
JP6126458B2 (ja) * 2013-05-22 2017-05-10 富士通株式会社 抵抗調整回路、及び、抵抗調整方法
US9571098B2 (en) 2014-08-11 2017-02-14 Samsung Electronics Co., Ltd. Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
US10679909B2 (en) * 2016-11-21 2020-06-09 Kla-Tencor Corporation System, method and non-transitory computer readable medium for tuning sensitivies of, and determining a process window for, a modulated wafer
CN108206037B (zh) * 2016-12-16 2021-01-15 晶豪科技股份有限公司 在存储器装置的zq校准中决定电阻校准方向的方法
KR20190075788A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 캘리브레이션 장치를 포함하는 스토리지 장치
EP3731411A4 (en) * 2019-01-18 2021-01-13 Shenzhen Goodix Technology Co., Ltd. SIGNAL GENERATION CIRCUIT, ASSOCIATED CHIP, FLOW METER AND PROCEDURE
US10630289B1 (en) * 2019-03-01 2020-04-21 Realtek Semiconductor Corp. On-die-termination circuit and control method for of the same
CN116107384B (zh) * 2021-11-11 2025-09-23 瑞昱半导体股份有限公司 具有自参考阻抗的集成电路
CN114915284A (zh) * 2022-05-31 2022-08-16 上海金脉电子科技有限公司 开关控制电路、电机驱动系统及车辆

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142610A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd コンパレ−タ回路
JPS6184110A (ja) * 1984-10-01 1986-04-28 Nec Corp 電圧比較器
JPS62269512A (ja) * 1986-05-19 1987-11-24 Nippon Telegr & Teleph Corp <Ntt> 電圧比較器
JPH06232706A (ja) * 1993-02-05 1994-08-19 Nec Corp 比較器
US6026456A (en) 1995-12-15 2000-02-15 Intel Corporation System utilizing distributed on-chip termination
JPH10261948A (ja) * 1997-03-17 1998-09-29 Nec Corp 出力インピーダンス自己補正回路付半導体集積回路
US6157206A (en) 1998-12-31 2000-12-05 Intel Corporation On-chip termination
KR100410536B1 (ko) * 2001-02-05 2003-12-18 삼성전자주식회사 터미네이션 회로의 임피던스 업데이트 장치 및 방법
ATE401694T1 (de) 2001-04-11 2008-08-15 Nxp Bv Offsetspannungskompensation mit hohem tastverhältnis für operationsverstärker
KR100403633B1 (ko) * 2001-08-10 2003-10-30 삼성전자주식회사 임피던스 제어회로
JP3702227B2 (ja) * 2002-01-09 2005-10-05 株式会社東芝 半導体装置
KR100468728B1 (ko) * 2002-04-19 2005-01-29 삼성전자주식회사 반도체 집적회로의 온-칩 터미네이터, 그 제어 회로 및 그제어 방법
KR100422451B1 (ko) * 2002-05-24 2004-03-11 삼성전자주식회사 온-다이 터미네이션 제어방법 및 그에 따른 제어회로
TW544995B (en) 2002-08-09 2003-08-01 Advanic Technologies Inc Flash A/D converter with new autozeroing and interpolation possessing negative impedance compensation
KR100464437B1 (ko) * 2002-11-20 2004-12-31 삼성전자주식회사 온칩 dc 전류 소모를 최소화할 수 있는 odt 회로와odt 방법 및 이를 구비하는 메모리장치를 채용하는메모리 시스템
KR100532426B1 (ko) * 2003-03-25 2005-11-30 삼성전자주식회사 온-칩 터미네이션 저항의 미스매치를 보상할 수 있는반도체 장치
KR100502664B1 (ko) * 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
US6924660B2 (en) * 2003-09-08 2005-08-02 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7205787B1 (en) * 2003-11-24 2007-04-17 Neascape, Inc. On-chip termination for a high-speed single-ended interface
KR100515068B1 (ko) * 2003-12-19 2005-09-16 주식회사 하이닉스반도체 반도체 기억 소자의 온 다이 터미네이션을 위한 회로 및방법
KR100528164B1 (ko) 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
KR100578649B1 (ko) * 2004-04-20 2006-05-11 주식회사 하이닉스반도체 온-다이 터미네이션 제어 회로 및 온-다이 터미네이션제어 신호 생성 방법
KR100532972B1 (ko) * 2004-04-28 2005-12-01 주식회사 하이닉스반도체 온 다이 터미네이션 임피던스 조절 장치
KR100670702B1 (ko) 2004-10-30 2007-01-17 주식회사 하이닉스반도체 온다이 터미네이션 회로를 구비한 반도체 메모리 장치
US7138823B2 (en) * 2005-01-20 2006-11-21 Micron Technology, Inc. Apparatus and method for independent control of on-die termination for output buffers of a memory device
US7218155B1 (en) * 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7221193B1 (en) * 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
KR100681879B1 (ko) * 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12143084B1 (en) 2023-04-18 2024-11-12 Nanya Technology Corporation Impedance adjusting circuit and impedance adjusting method for zero quotient calibration
TWI864764B (zh) * 2023-04-18 2024-12-01 南亞科技股份有限公司 用於阻抗校準的阻抗調整電路及阻抗調整方法

Also Published As

Publication number Publication date
JP2007195168A (ja) 2007-08-02
US7288959B1 (en) 2007-10-30
US20070164780A1 (en) 2007-07-19
CN101025995A (zh) 2007-08-29
TW200731662A (en) 2007-08-16
KR100681879B1 (ko) 2007-02-15
JP2013048459A (ja) 2013-03-07
US7888963B2 (en) 2011-02-15
US20080001624A1 (en) 2008-01-03
CN101025995B (zh) 2010-04-14

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