JP2006523963A - 磁気抵抗ランダムアクセスメモリ装置及びその製造方法 - Google Patents

磁気抵抗ランダムアクセスメモリ装置及びその製造方法 Download PDF

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Publication number
JP2006523963A
JP2006523963A JP2006513082A JP2006513082A JP2006523963A JP 2006523963 A JP2006523963 A JP 2006523963A JP 2006513082 A JP2006513082 A JP 2006513082A JP 2006513082 A JP2006513082 A JP 2006513082A JP 2006523963 A JP2006523963 A JP 2006523963A
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Japan
Prior art keywords
tunnel junction
magnetic tunnel
element device
layer
conductive layer
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Japanese (ja)
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JP2006523963A5 (enExample
Inventor
グリンコウィッチ、グレゴリー
デエレラ、マーク
エイ． ダーラム、マーク
ジェイ． トレイシー、クラレンス
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NXP USA Inc
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NXP USA Inc
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Publication of JP2006523963A publication Critical patent/JP2006523963A/ja
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Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
JP2006513082A 2003-04-16 2004-04-16 磁気抵抗ランダムアクセスメモリ装置及びその製造方法 Pending JP2006523963A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/417,851 US6784510B1 (en) 2003-04-16 2003-04-16 Magnetoresistive random access memory device structures
PCT/US2004/011864 WO2004095459A2 (en) 2003-04-16 2004-04-16 Magnetoresistive ram device and methods for fabricating

Publications (2)

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JP2006523963A true JP2006523963A (ja) 2006-10-19
JP2006523963A5 JP2006523963A5 (enExample) 2007-06-07

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JP2006513082A Pending JP2006523963A (ja) 2003-04-16 2004-04-16 磁気抵抗ランダムアクセスメモリ装置及びその製造方法

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Country Link
US (2) US6784510B1 (enExample)
JP (1) JP2006523963A (enExample)
KR (1) KR101036722B1 (enExample)
CN (1) CN100449788C (enExample)
TW (1) TWI349980B (enExample)
WO (1) WO2004095459A2 (enExample)

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US8885396B2 (en) 2011-09-07 2014-11-11 Kabushiki Kaisha Toshiba Memory device and method for manufacturing the same

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US7087972B1 (en) * 2005-01-31 2006-08-08 Freescale Semiconductor, Inc. Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same
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US8521314B2 (en) * 2006-11-01 2013-08-27 Dolby Laboratories Licensing Corporation Hierarchical control path with constraints for audio dynamics processing
KR100990143B1 (ko) * 2008-07-03 2010-10-29 주식회사 하이닉스반도체 자기터널접합 장치, 이를 구비하는 메모리 셀 및 그제조방법
US8208290B2 (en) * 2009-08-26 2012-06-26 Qualcomm Incorporated System and method to manufacture magnetic random access memory
US8390283B2 (en) 2009-09-25 2013-03-05 Everspin Technologies, Inc. Three axis magnetic field sensor
US8518734B2 (en) 2010-03-31 2013-08-27 Everspin Technologies, Inc. Process integration of a single chip three axis magnetic field sensor
CN102376737B (zh) * 2010-08-24 2014-03-19 中芯国际集成电路制造(北京)有限公司 嵌入mram的集成电路及该集成电路的制备方法
US8895323B2 (en) * 2011-12-19 2014-11-25 Lam Research Corporation Method of forming a magnetoresistive random-access memory device
US8456883B1 (en) * 2012-05-29 2013-06-04 Headway Technologies, Inc. Method of spin torque MRAM process integration
JP6148450B2 (ja) * 2012-10-29 2017-06-14 株式会社東芝 積層構造、スピントランジスタおよびリコンフィギャラブル論理回路
US10522591B2 (en) * 2013-03-13 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of magneto-resistive random access memory and capacitor
CN104122514B (zh) * 2013-04-24 2018-01-02 上海矽睿科技有限公司 磁传感装置的制备工艺
KR102399342B1 (ko) * 2015-08-21 2022-05-19 삼성전자주식회사 메모리 장치 및 그 제조 방법
WO2017155507A1 (en) * 2016-03-07 2017-09-14 Intel Corporation Approaches for embedding spin hall mtj devices into a logic processor and the resulting structures
US11469268B2 (en) * 2016-03-18 2022-10-11 Intel Corporation Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures
CN109713120A (zh) * 2017-10-25 2019-05-03 上海磁宇信息科技有限公司 一种磁性随机存储器单元阵列及周边电路连线的制造方法
CN109713119A (zh) * 2017-10-25 2019-05-03 上海磁宇信息科技有限公司 一种磁性随机存储器单元阵列及周边电路连线的制造方法
CN109873009B (zh) * 2017-12-01 2023-09-22 上海磁宇信息科技有限公司 一种使用接地哑元的mram芯片
CN109994600B (zh) * 2017-12-29 2022-11-04 上海磁宇信息科技有限公司 一种磁性随机存储器的制作方法
KR20190122421A (ko) * 2018-04-20 2019-10-30 삼성전자주식회사 반도체 소자
CN111668368B (zh) * 2019-03-08 2023-12-29 上海磁宇信息科技有限公司 一种假磁性隧道结单元结构制备方法
CN111816761B (zh) * 2019-04-11 2024-04-12 上海磁宇信息科技有限公司 一种赝磁性隧道结单元
CN111816763B (zh) * 2019-04-11 2024-04-23 上海磁宇信息科技有限公司 一种磁性隧道结存储阵列单元及其外围电路的制备方法
CN111863865B (zh) * 2019-04-24 2024-04-12 上海磁宇信息科技有限公司 一种赝磁性隧道结单元
CN111987216B (zh) * 2019-05-23 2024-04-16 上海磁宇信息科技有限公司 一种替代通孔的赝磁性隧道结单元制备方法

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JP2002176150A (ja) * 2000-09-27 2002-06-21 Canon Inc 磁気抵抗効果を用いた不揮発固体メモリ素子およびメモリとその記録再生方法
JP2002533863A (ja) * 1998-12-18 2002-10-08 モトローラ・インコーポレイテッド 参照メモリ・アレイを有する磁気ランダム・アクセス・メモリ
JP2002359356A (ja) * 2001-03-29 2002-12-13 Toshiba Corp 半導体記憶装置
JP2003060165A (ja) * 2001-08-08 2003-02-28 Toshiba Corp 半導体記憶装置

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JP2002533863A (ja) * 1998-12-18 2002-10-08 モトローラ・インコーポレイテッド 参照メモリ・アレイを有する磁気ランダム・アクセス・メモリ
JP2002176150A (ja) * 2000-09-27 2002-06-21 Canon Inc 磁気抵抗効果を用いた不揮発固体メモリ素子およびメモリとその記録再生方法
JP2002359356A (ja) * 2001-03-29 2002-12-13 Toshiba Corp 半導体記憶装置
JP2003060165A (ja) * 2001-08-08 2003-02-28 Toshiba Corp 半導体記憶装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8885396B2 (en) 2011-09-07 2014-11-11 Kabushiki Kaisha Toshiba Memory device and method for manufacturing the same

Also Published As

Publication number Publication date
WO2004095459A2 (en) 2004-11-04
US20040257902A1 (en) 2004-12-23
TW200509312A (en) 2005-03-01
CN100449788C (zh) 2009-01-07
WO2004095459A3 (en) 2005-03-24
CN1774816A (zh) 2006-05-17
KR20060009844A (ko) 2006-02-01
TWI349980B (en) 2011-10-01
US6784510B1 (en) 2004-08-31
KR101036722B1 (ko) 2011-05-24
US6890770B2 (en) 2005-05-10

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