JP2006140445A - 複合材料ウェーハの製造方法 - Google Patents
複合材料ウェーハの製造方法 Download PDFInfo
- Publication number
- JP2006140445A JP2006140445A JP2005270897A JP2005270897A JP2006140445A JP 2006140445 A JP2006140445 A JP 2006140445A JP 2005270897 A JP2005270897 A JP 2005270897A JP 2005270897 A JP2005270897 A JP 2005270897A JP 2006140445 A JP2006140445 A JP 2006140445A
- Authority
- JP
- Japan
- Prior art keywords
- donor substrate
- layer
- substrate
- initial
- handle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 235000012431 wafers Nutrition 0.000 title abstract description 42
- 150000001875 compounds Chemical class 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 238000000034 method Methods 0.000 claims abstract description 59
- 230000005693 optoelectronics Effects 0.000 claims abstract description 6
- 230000003287 optical effect Effects 0.000 claims abstract description 3
- 239000002131 composite material Substances 0.000 claims description 26
- 230000001681 protective effect Effects 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 230000006872 improvement Effects 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 25
- 238000000926 separation method Methods 0.000 abstract description 13
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 20
- 229910002601 GaN Inorganic materials 0.000 description 12
- 239000010408 film Substances 0.000 description 12
- 230000007704 transition Effects 0.000 description 11
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/93—Ternary or quaternary semiconductor comprised of elements from three different groups, e.g. I-III-V
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Physical Vapour Deposition (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
【解決手段】初期ドナー基板1に所定分離領域4を形成する工程と、ハンドル基板2に初期ドナー基板1を取り付ける工程と、ハンドル基板2上へ初期ドナー基板1の層6を転移して複合材料ウェーハ10を形成するために所定分離領域4においてドナー基板1を取り外す工程を備える。取外し工程後に、初期ドナー基板1の厚さを少なくとも部分的に回復するためにドナー基板の残余部9上に層12を堆積し、初期ドナー基板1として堆積層12を有するドナー基板を再使用する。
【選択図】図1
Description
転位は成長中、あるレベルで途絶える傾向があり、そのため追加成長材料は、より低い転位密度を示す。このように、ドナー基板材料の品質は向上し、そのため転移層は市場で入手できる標準ドナー基板により達成される転移層と比較して、品質においてより良好である。
Claims (14)
- a)初期ドナー基板(1)を設ける工程と、
b)前記初期ドナー基板(1)に所定分離領域(4)を形成する工程と、
c)ハンドル基板(2)に前記初期ドナー基板(1)を取り付ける工程と、
d)前記初期ドナー基板(1)の層(6)を前記ハンドル基板(2)上に転移して複合材料ウェーハ(10)を形成するために、前記所定分離領域(4)において前記ドナー基板(1)を取り外す工程と、
を備える複合材料ウェーハの製造方法において、
e)前記初期ドナー基板(1)の厚さを少なくとも部分的に回復するために、前記取り外し工程後、前記ドナー基板の残余部(9)上に層(12)を堆積する工程と、
f)前記堆積層(12)を有する前記ドナー基板(1)を工程a)における前記初期ドナー基板(1)として再使用する工程と、
を備えることを特徴とする複合材料ウェーハの製造方法。 - 前記工程e)を実行する前に前記工程a)〜工程d)を少なくとも2回繰り返す工程において、
繰り返される工程a)において、前記取り外したドナー基板の残余部を初期ドナー基板(1)として再使用する請求項1に記載の方法。 - 前記工程a)〜工程d)は、前記初期ドナー基板(1)が所定最低厚さに達するまで繰り返される請求項2に記載の方法。
- 前記工程e)における前記層(12)は、ホモエピタキシャルに堆積される請求項1〜3のいずれか1項に記載の方法。
- 前記工程e)において、前記ホモエピタキシャル層(12)はMOCVD、HVPEまたはMBE方法を使用して設けられ、それにより、前記初期ドナー基板(1)における転位密度と比較して前記ホモエピタキシャル層(12)における転位密度の改善、特に1×107/cm2未満の転位密度、特に1×106/cm2未満を達成する請求項4に記載の方法。
- 前記工程e)は、ドナー基板の残余部(9)の、取外しが起きた表面(11)とは反対側の表面(15)上に前記層(12)を設ける工程を備える請求項1〜5のいずれか1項に記載の方法。
- 前記工程e)に先立ち、特に酸化物及び/または窒化物層を使用して取外しが起きた前記表面側(11)に保護膜(30)を設ける工程を備える請求項6に記載の方法。
- 前記層(12)を有する前記ドナー基板(1)を初期ドナー基板(1)として再使用することに先立ち、前記保護膜(30)を除去する工程を更に備える請求項7に記載の方法。
- 前記工程e)において、前記層を設ける前記ドナー基板の残余部(9)の表面側(11、15)を研磨及び/または洗浄する工程を更に備える請求項1〜8のいずれか1項に記載の方法。
- 前記ドナー基板(1)は、GaN、SiC、Ge、AlNまたはダイヤモンドのグループ一つである請求項1〜9のいずれか1項に記載の方法。
- 前記ハンドル基板(2)は、単結晶または多結晶材料であり、特にSi、GaAs、ZnO、SiC、AlNのグループの一つである請求項1〜10のいずれか1項に記載の方法。
- 前記ハンドル基板(2)は、ガラスまたはセラミック材料である請求項1〜10のいずれか1項に記載の方法。
- 前記工程c)に先立ち、前記ドナー基板(1)に取り付けられる前記ハンドル基板(2)の表面(7)上に絶縁層、特にSiO2またはSi3N4、または導体層を設ける工程を更に備える請求項1〜12のいずれか1項に記載の方法。
- 請求項1〜13のいずれか1項により製造された前記複合材料ウェーハの少なくとも一部を備える電子的、光電子的または光学的部品。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04292655A EP1667223B1 (en) | 2004-11-09 | 2004-11-09 | Method for manufacturing compound material wafers |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006140445A true JP2006140445A (ja) | 2006-06-01 |
JP4489671B2 JP4489671B2 (ja) | 2010-06-23 |
Family
ID=34931512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005270897A Active JP4489671B2 (ja) | 2004-11-09 | 2005-09-16 | 複合材料ウェーハの製造方法 |
Country Status (9)
Country | Link |
---|---|
US (3) | US7531428B2 (ja) |
EP (2) | EP1962340A3 (ja) |
JP (1) | JP4489671B2 (ja) |
KR (1) | KR100746182B1 (ja) |
CN (2) | CN100426459C (ja) |
AT (1) | ATE420461T1 (ja) |
DE (1) | DE602004018951D1 (ja) |
SG (1) | SG122972A1 (ja) |
TW (2) | TWI303842B (ja) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008010766A (ja) * | 2006-06-30 | 2008-01-17 | Sumitomo Electric Ind Ltd | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 |
JP2008205387A (ja) * | 2007-02-22 | 2008-09-04 | Tokyo Ohka Kogyo Co Ltd | サポートプレートの処理方法 |
KR20090093887A (ko) * | 2008-02-29 | 2009-09-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 단결정 박막을 갖는 기판의 제조 방법 |
JP2009231816A (ja) * | 2008-02-29 | 2009-10-08 | Shin Etsu Chem Co Ltd | 単結晶薄膜を有する基板の製造方法 |
WO2010082396A1 (ja) * | 2009-01-16 | 2010-07-22 | 住友電気工業株式会社 | 発光素子用基板 |
JP2010232609A (ja) * | 2009-03-30 | 2010-10-14 | Hitachi Cable Ltd | Iii族窒化物半導体複合基板、iii族窒化物半導体基板、及びiii族窒化物半導体複合基板の製造方法 |
WO2010127320A2 (en) * | 2009-04-30 | 2010-11-04 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
JP2011077102A (ja) * | 2009-09-29 | 2011-04-14 | Toyoda Gosei Co Ltd | ウエハ、iii族窒化物系化合物半導体素子、及びそれらの製造方法 |
JP2012156553A (ja) * | 2012-05-10 | 2012-08-16 | Tokyo Ohka Kogyo Co Ltd | サポートプレートの処理方法 |
JP2013084781A (ja) * | 2011-10-11 | 2013-05-09 | Nippon Telegr & Teleph Corp <Ntt> | 半導体積層構造の製造方法 |
WO2014207988A1 (ja) | 2013-06-26 | 2014-12-31 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
WO2015033516A1 (ja) | 2013-09-05 | 2015-03-12 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
WO2015103274A1 (en) * | 2013-12-30 | 2015-07-09 | Veeco Instruments, Inc. | Engineered substrates for use in crystalline-nitride based devices |
US9418963B2 (en) | 2012-09-25 | 2016-08-16 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
US9589801B2 (en) | 2011-10-31 | 2017-03-07 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization |
JP2019528570A (ja) * | 2016-08-11 | 2019-10-10 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | 成長基板上にエピタキシャル層を生成する方法 |
JP2023513258A (ja) * | 2020-02-14 | 2023-03-30 | 京セラ株式会社 | 基板の再利用方法、半導体素子の製造方法、および半導体素子 |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
US20070023761A1 (en) * | 2005-07-26 | 2007-02-01 | Robbins Virginia M | Silicon carbon germanium (SiCGe) substrate for a group III nitride-based device |
JP4873467B2 (ja) * | 2006-07-27 | 2012-02-08 | 独立行政法人産業技術総合研究所 | オフ角を有する単結晶基板の製造方法 |
EP2155769B1 (en) * | 2007-05-04 | 2012-06-27 | Katholieke Universiteit Leuven KU Leuven Research & Development | Tissue degeneration protection |
JP5143477B2 (ja) * | 2007-05-31 | 2013-02-13 | 信越化学工業株式会社 | Soiウエーハの製造方法 |
US20090061593A1 (en) * | 2007-08-28 | 2009-03-05 | Kishor Purushottam Gadkaree | Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment |
US20120167819A1 (en) * | 2007-10-06 | 2012-07-05 | Solexel, Inc. | Method for reconstructing a semiconductor template |
JP5522917B2 (ja) * | 2007-10-10 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Soi基板の製造方法 |
CN101842910B (zh) * | 2007-11-01 | 2013-03-27 | 株式会社半导体能源研究所 | 用于制造光电转换器件的方法 |
WO2009063288A1 (en) * | 2007-11-15 | 2009-05-22 | S.O.I.Tec Silicon On Insulator Technologies | Semiconductor structure having a protective layer |
FR2928775B1 (fr) * | 2008-03-11 | 2011-12-09 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semiconducteur sur isolant |
WO2009141724A1 (en) * | 2008-05-23 | 2009-11-26 | S.O.I.Tec Silicon On Insulator Technologies | Formation of substantially pit free indium gallium nitride |
EP2329056B1 (en) | 2008-08-28 | 2012-12-19 | Soitec | Uv absorption based monitor and control of chloride gas stream |
US8679942B2 (en) * | 2008-11-26 | 2014-03-25 | Soitec | Strain engineered composite semiconductor substrates and methods of forming same |
US8278167B2 (en) | 2008-12-18 | 2012-10-02 | Micron Technology, Inc. | Method and structure for integrating capacitor-less memory cell with logic |
US8198172B2 (en) * | 2009-02-25 | 2012-06-12 | Micron Technology, Inc. | Methods of forming integrated circuits using donor and acceptor substrates |
US8178396B2 (en) * | 2009-03-11 | 2012-05-15 | Micron Technology, Inc. | Methods for forming three-dimensional memory devices, and related structures |
US8871109B2 (en) * | 2009-04-28 | 2014-10-28 | Gtat Corporation | Method for preparing a donor surface for reuse |
KR20120032487A (ko) * | 2009-06-24 | 2012-04-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 재생 처리 및 soi 기판의 제작 방법 |
US8278187B2 (en) * | 2009-06-24 | 2012-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments |
WO2011024619A1 (en) * | 2009-08-25 | 2011-03-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate |
US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
KR101731809B1 (ko) * | 2009-10-09 | 2017-05-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 재생 방법, 재생된 반도체 기판의 제조 방법, 및 soi 기판의 제조 방법 |
US8461566B2 (en) | 2009-11-02 | 2013-06-11 | Micron Technology, Inc. | Methods, structures and devices for increasing memory density |
KR101460086B1 (ko) * | 2009-12-15 | 2014-11-10 | 소이텍 | 기판의 재활용 공정 |
US9012253B2 (en) * | 2009-12-16 | 2015-04-21 | Micron Technology, Inc. | Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods |
WO2011084381A2 (en) * | 2009-12-21 | 2011-07-14 | Applied Materials, Inc. | Cleaning optimization of pecvd solar films |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US8288795B2 (en) | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
US8513722B2 (en) * | 2010-03-02 | 2013-08-20 | Micron Technology, Inc. | Floating body cell structures, devices including same, and methods for forming same |
US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US8609453B2 (en) * | 2010-11-22 | 2013-12-17 | International Business Machines Corporation | Low cost solar cell manufacture method employing a reusable substrate |
US8436363B2 (en) | 2011-02-03 | 2013-05-07 | Soitec | Metallic carrier for layer transfer and methods for forming the same |
US9082948B2 (en) | 2011-02-03 | 2015-07-14 | Soitec | Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods |
US9142412B2 (en) | 2011-02-03 | 2015-09-22 | Soitec | Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods |
FR2971365B1 (fr) * | 2011-02-08 | 2013-02-22 | Soitec Silicon On Insulator | Méthode de recyclage d'un substrat source |
US8598621B2 (en) | 2011-02-11 | 2013-12-03 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
US8952418B2 (en) | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
US20130137244A1 (en) * | 2011-05-26 | 2013-05-30 | Solexel, Inc. | Method and apparatus for reconditioning a carrier wafer for reuse |
US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
KR20130049484A (ko) * | 2011-11-04 | 2013-05-14 | 삼성코닝정밀소재 주식회사 | 박막 접합 기판 제조방법 |
WO2013093590A1 (en) | 2011-12-23 | 2013-06-27 | Soitec | Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods |
US8841161B2 (en) | 2012-02-05 | 2014-09-23 | GTAT.Corporation | Method for forming flexible solar cells |
US8916954B2 (en) | 2012-02-05 | 2014-12-23 | Gtat Corporation | Multi-layer metal support |
JP2013247362A (ja) * | 2012-05-29 | 2013-12-09 | Samsung Corning Precision Materials Co Ltd | 半導体素子用薄膜貼り合わせ基板の製造方法 |
CN104703939A (zh) | 2012-06-29 | 2015-06-10 | 康宁股份有限公司 | 用于半导体加工的玻璃陶瓷基材 |
US8785294B2 (en) | 2012-07-26 | 2014-07-22 | Gtat Corporation | Silicon carbide lamina |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
CN105051919A (zh) * | 2013-01-16 | 2015-11-11 | Qmat股份有限公司 | 用于形成光电器件的技术 |
US11721547B2 (en) * | 2013-03-14 | 2023-08-08 | Infineon Technologies Ag | Method for manufacturing a silicon carbide substrate for an electrical silicon carbide device, a silicon carbide substrate and an electrical silicon carbide device |
FR3007892B1 (fr) * | 2013-06-27 | 2015-07-31 | Commissariat Energie Atomique | Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive |
WO2015009669A1 (en) | 2013-07-16 | 2015-01-22 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates |
EP3434816A4 (en) * | 2016-03-23 | 2019-10-30 | Tokuyama Corporation | METHOD FOR MANUFACTURING A SINGLE CRYSTAL SUBSTRATE OF ALUMINUM NITRIDE |
US10679852B2 (en) * | 2016-06-13 | 2020-06-09 | QROMIS, Inc. | Multi-deposition process for high quality gallium nitride device manufacturing |
US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
US20180033609A1 (en) * | 2016-07-28 | 2018-02-01 | QMAT, Inc. | Removal of non-cleaved/non-transferred material from donor substrate |
DE102018111450B4 (de) | 2018-05-14 | 2024-06-20 | Infineon Technologies Ag | Verfahren zum Verarbeiten eines Breiter-Bandabstand-Halbleiterwafers, Verfahren zum Bilden einer Mehrzahl von dünnen Breiter-Bandabstand-Halbleiterwafern und Breiter-Bandabstand-Halbleiterwafer |
WO2020010056A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
CN115943489A (zh) | 2020-03-19 | 2023-04-07 | 隔热半导体粘合技术公司 | 用于直接键合结构的尺寸补偿控制 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09162090A (ja) * | 1995-10-06 | 1997-06-20 | Canon Inc | 半導体基体とその製造方法 |
JPH10335617A (ja) * | 1997-05-30 | 1998-12-18 | Denso Corp | 半導体基板の製造方法 |
JPH1174209A (ja) * | 1997-08-27 | 1999-03-16 | Denso Corp | 半導体基板の製造方法 |
JP2000223681A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基板及びその製造方法 |
JP2000349267A (ja) * | 1999-03-26 | 2000-12-15 | Canon Inc | 半導体部材の作製方法 |
WO2004007816A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating substrates, in particular for optics, electronics or optoelectronics________________________________________ |
WO2004019404A2 (en) * | 2002-08-26 | 2004-03-04 | S.O.I.Tec Silicon On Insulator Technologies | Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom |
JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US38466A (en) * | 1863-05-12 | Improved medicine for piles | ||
IT1210982B (it) * | 1981-02-03 | 1989-09-29 | Giuseppe Stefano Piana | Capsula a perdere, per la confezione di preparati idrosolubili in dosi, atti a consentire la preparazione di bevande calde in genere. |
FI83197C (fi) * | 1984-10-23 | 1991-06-10 | Mars G B Ltd | Dryckpaose. |
JPH05275332A (ja) * | 1992-03-26 | 1993-10-22 | Shimadzu Corp | ヘテロエピタキシャル膜の製膜方法 |
US20030087503A1 (en) | 1994-03-10 | 2003-05-08 | Canon Kabushiki Kaisha | Process for production of semiconductor substrate |
DE69737086T2 (de) * | 1996-08-27 | 2007-05-16 | Seiko Epson Corp. | Trennverfahren, verfahren zur übertragung eines dünnfilmbauelements, und unter verwendung des übertragungsverfahrens hergestelltes flüssigkristall-anzeigebauelement |
US6127199A (en) * | 1996-11-12 | 2000-10-03 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
USRE38466E1 (en) | 1996-11-12 | 2004-03-16 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
EP0874405A3 (en) * | 1997-03-25 | 2004-09-15 | Mitsubishi Cable Industries, Ltd. | GaN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof |
JP3492142B2 (ja) * | 1997-03-27 | 2004-02-03 | キヤノン株式会社 | 半導体基材の製造方法 |
US6251754B1 (en) * | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
FR2774214B1 (fr) | 1998-01-28 | 2002-02-08 | Commissariat Energie Atomique | PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US6328796B1 (en) | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
US6468923B1 (en) * | 1999-03-26 | 2002-10-22 | Canon Kabushiki Kaisha | Method of producing semiconductor member |
WO2001006564A1 (en) * | 1999-07-15 | 2001-01-25 | Shin-Etsu Handotai Co., Ltd. | Method for producing bonded wafer and bonded wafer |
US6500732B1 (en) | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
US6223650B1 (en) * | 1999-09-30 | 2001-05-01 | Robert M. Stuck | Apparatus for conveyorized toasting of breads and like food items |
JP3943782B2 (ja) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
US6475882B1 (en) * | 1999-12-20 | 2002-11-05 | Nitride Semiconductors Co., Ltd. | Method for producing GaN-based compound semiconductor and GaN-based compound semiconductor device |
CN1292494C (zh) | 2000-04-26 | 2006-12-27 | 奥斯兰姆奥普托半导体有限责任公司 | 发光半导体元件及其制造方法 |
FR2817394B1 (fr) | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
FR2817395B1 (fr) | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
US6740345B2 (en) * | 2000-12-22 | 2004-05-25 | Edward Zhihua Cai | Beverage making cartridge |
US6497763B2 (en) | 2001-01-19 | 2002-12-24 | The United States Of America As Represented By The Secretary Of The Navy | Electronic device with composite substrate |
JP3826825B2 (ja) * | 2001-04-12 | 2006-09-27 | 住友電気工業株式会社 | 窒化ガリウム結晶への酸素ドーピング方法と酸素ドープされたn型窒化ガリウム単結晶基板 |
JP2003022989A (ja) * | 2001-07-09 | 2003-01-24 | Sumitomo Mitsubishi Silicon Corp | エピタキシャル半導体ウェーハ及びその製造方法 |
FR2828762B1 (fr) | 2001-08-14 | 2003-12-05 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique |
JP2003101025A (ja) * | 2001-09-26 | 2003-04-04 | Toshiba Corp | 半導体装置 |
FR2834124B1 (fr) | 2001-12-20 | 2005-05-20 | Osram Opto Semiconductors Gmbh | Procede de production de couches semi-conductrices |
FR2834123B1 (fr) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report |
JP2003204048A (ja) | 2002-01-09 | 2003-07-18 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
US7008857B2 (en) * | 2002-08-26 | 2006-03-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom |
CN100557785C (zh) * | 2002-08-26 | 2009-11-04 | S.O.I.Tec绝缘体上硅技术公司 | 具有缓冲结构的晶片的再循环 |
US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
-
2004
- 2004-11-09 AT AT04292655T patent/ATE420461T1/de not_active IP Right Cessation
- 2004-11-09 EP EP08007333A patent/EP1962340A3/en not_active Withdrawn
- 2004-11-09 DE DE602004018951T patent/DE602004018951D1/de active Active
- 2004-11-09 EP EP04292655A patent/EP1667223B1/en active Active
-
2005
- 2005-03-18 US US11/084,553 patent/US7531428B2/en active Active
- 2005-08-31 TW TW094129941A patent/TWI303842B/zh active
- 2005-08-31 TW TW096148068A patent/TWI367544B/zh active
- 2005-09-16 JP JP2005270897A patent/JP4489671B2/ja active Active
- 2005-11-03 KR KR1020050104993A patent/KR100746182B1/ko active IP Right Grant
- 2005-11-08 CN CNB2005101156304A patent/CN100426459C/zh active Active
- 2005-11-08 SG SG200508509A patent/SG122972A1/en unknown
- 2005-11-08 CN CN200810002207.7A patent/CN101221895B/zh active Active
-
2009
- 2009-03-31 US US12/415,085 patent/US7851330B2/en active Active
-
2010
- 2010-11-04 US US12/939,590 patent/US7968909B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09162090A (ja) * | 1995-10-06 | 1997-06-20 | Canon Inc | 半導体基体とその製造方法 |
JPH10335617A (ja) * | 1997-05-30 | 1998-12-18 | Denso Corp | 半導体基板の製造方法 |
JPH1174209A (ja) * | 1997-08-27 | 1999-03-16 | Denso Corp | 半導体基板の製造方法 |
JP2000223681A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基板及びその製造方法 |
JP2000349267A (ja) * | 1999-03-26 | 2000-12-15 | Canon Inc | 半導体部材の作製方法 |
WO2004007816A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating substrates, in particular for optics, electronics or optoelectronics________________________________________ |
WO2004019404A2 (en) * | 2002-08-26 | 2004-03-04 | S.O.I.Tec Silicon On Insulator Technologies | Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom |
JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8143140B2 (en) | 2006-06-30 | 2012-03-27 | Sumitomo Electric Industries, Ltd. | Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same |
JP2008010766A (ja) * | 2006-06-30 | 2008-01-17 | Sumitomo Electric Ind Ltd | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 |
JP2008205387A (ja) * | 2007-02-22 | 2008-09-04 | Tokyo Ohka Kogyo Co Ltd | サポートプレートの処理方法 |
KR20090093887A (ko) * | 2008-02-29 | 2009-09-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 단결정 박막을 갖는 기판의 제조 방법 |
JP2009231816A (ja) * | 2008-02-29 | 2009-10-08 | Shin Etsu Chem Co Ltd | 単結晶薄膜を有する基板の製造方法 |
KR101581044B1 (ko) | 2008-02-29 | 2015-12-30 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 단결정 박막을 갖는 기판의 제조 방법 |
WO2010082396A1 (ja) * | 2009-01-16 | 2010-07-22 | 住友電気工業株式会社 | 発光素子用基板 |
JP2010165927A (ja) * | 2009-01-16 | 2010-07-29 | Sumitomo Electric Ind Ltd | 発光素子用基板 |
JP2010232609A (ja) * | 2009-03-30 | 2010-10-14 | Hitachi Cable Ltd | Iii族窒化物半導体複合基板、iii族窒化物半導体基板、及びiii族窒化物半導体複合基板の製造方法 |
WO2010127320A3 (en) * | 2009-04-30 | 2011-01-13 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
US9018077B2 (en) | 2009-04-30 | 2015-04-28 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
WO2010127320A2 (en) * | 2009-04-30 | 2010-11-04 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
JP2011077102A (ja) * | 2009-09-29 | 2011-04-14 | Toyoda Gosei Co Ltd | ウエハ、iii族窒化物系化合物半導体素子、及びそれらの製造方法 |
JP2013084781A (ja) * | 2011-10-11 | 2013-05-09 | Nippon Telegr & Teleph Corp <Ntt> | 半導体積層構造の製造方法 |
US9589801B2 (en) | 2011-10-31 | 2017-03-07 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization |
JP2012156553A (ja) * | 2012-05-10 | 2012-08-16 | Tokyo Ohka Kogyo Co Ltd | サポートプレートの処理方法 |
US9418963B2 (en) | 2012-09-25 | 2016-08-16 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
KR20160023712A (ko) | 2013-06-26 | 2016-03-03 | 신에쯔 한도타이 가부시키가이샤 | 접합 웨이퍼의 제조방법 |
WO2014207988A1 (ja) | 2013-06-26 | 2014-12-31 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US9859149B2 (en) | 2013-06-26 | 2018-01-02 | Shin-Etsu Handotai Co., Ltd. | Method of producing bonded wafer with uniform thickness distribution |
JP2015053332A (ja) * | 2013-09-05 | 2015-03-19 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
KR20160052551A (ko) | 2013-09-05 | 2016-05-12 | 신에쯔 한도타이 가부시키가이샤 | 접합 웨이퍼의 제조방법 |
WO2015033516A1 (ja) | 2013-09-05 | 2015-03-12 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US9679800B2 (en) | 2013-09-05 | 2017-06-13 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded wafer |
WO2015103274A1 (en) * | 2013-12-30 | 2015-07-09 | Veeco Instruments, Inc. | Engineered substrates for use in crystalline-nitride based devices |
US9761671B2 (en) | 2013-12-30 | 2017-09-12 | Veeco Instruments, Inc. | Engineered substrates for use in crystalline-nitride based devices |
JP2019528570A (ja) * | 2016-08-11 | 2019-10-10 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | 成長基板上にエピタキシャル層を生成する方法 |
JP2023513258A (ja) * | 2020-02-14 | 2023-03-30 | 京セラ株式会社 | 基板の再利用方法、半導体素子の製造方法、および半導体素子 |
JP7441957B2 (ja) | 2020-02-14 | 2024-03-01 | 京セラ株式会社 | 基板再利用方法および半導体素子の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20060099776A1 (en) | 2006-05-11 |
US7851330B2 (en) | 2010-12-14 |
TWI303842B (en) | 2008-12-01 |
TWI367544B (en) | 2012-07-01 |
TW200824037A (en) | 2008-06-01 |
CN1790620A (zh) | 2006-06-21 |
CN101221895A (zh) | 2008-07-16 |
JP4489671B2 (ja) | 2010-06-23 |
KR100746182B1 (ko) | 2007-08-03 |
EP1667223B1 (en) | 2009-01-07 |
US20110049528A1 (en) | 2011-03-03 |
ATE420461T1 (de) | 2009-01-15 |
US20090191719A1 (en) | 2009-07-30 |
US7531428B2 (en) | 2009-05-12 |
EP1962340A3 (en) | 2009-12-23 |
EP1962340A2 (en) | 2008-08-27 |
TW200616014A (en) | 2006-05-16 |
DE602004018951D1 (de) | 2009-02-26 |
US7968909B2 (en) | 2011-06-28 |
CN101221895B (zh) | 2014-04-23 |
CN100426459C (zh) | 2008-10-15 |
SG122972A1 (en) | 2006-06-29 |
KR20060052446A (ko) | 2006-05-19 |
EP1667223A1 (en) | 2006-06-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4489671B2 (ja) | 複合材料ウェーハの製造方法 | |
KR100805469B1 (ko) | 특히 광학, 전자 공학 또는 광전자 공학용의 기판 제조방법, 및 이 방법에 의한 기판 | |
JP4733633B2 (ja) | エピタキシャル基板の製造方法 | |
JP5031365B2 (ja) | エピタキシャル成長層の形成方法 | |
US8154022B2 (en) | Process for fabricating a structure for epitaxy without an exclusion zone | |
US7538010B2 (en) | Method of fabricating an epitaxially grown layer | |
JP5031364B2 (ja) | エピタキシャル成長層の形成方法 | |
US8481407B2 (en) | Processes for fabricating heterostructures | |
JP2008537341A (ja) | 自立(Al,In,Ga)Nウェーハ製作のためのウェーハ分離技術 | |
US20050003641A1 (en) | Method for fabricating an epitaxial substrate | |
US8785293B2 (en) | Adaptation of the lattice parameter of a layer of strained material | |
EP2466626A2 (en) | Relaxation and transfer of strained material layers | |
CN109585615B (zh) | 将氮化镓外延层从衬底上剥离的方法 | |
KR101236213B1 (ko) | 질화갈륨 기판을 형성하기 위한 프로세스 | |
KR20130051232A (ko) | 박막 접합 기판 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090707 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091007 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20091007 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091016 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100105 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100218 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100316 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100331 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130409 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4489671 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140409 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |