WO2015033516A1 - 貼り合わせウェーハの製造方法 - Google Patents
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- WO2015033516A1 WO2015033516A1 PCT/JP2014/004038 JP2014004038W WO2015033516A1 WO 2015033516 A1 WO2015033516 A1 WO 2015033516A1 JP 2014004038 W JP2014004038 W JP 2014004038W WO 2015033516 A1 WO2015033516 A1 WO 2015033516A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
Definitions
- the present invention relates to a method for producing a bonded wafer using an ion implantation separation method, and in particular, a reproduction obtained by subjecting a separation wafer produced as a by-product when a bonded wafer is produced by an ion implantation separation method to a regeneration process.
- the present invention relates to a method for manufacturing a bonded wafer by ion implantation separation using a wafer.
- a method for manufacturing an SOI wafer is a method of manufacturing an SOI wafer by peeling an ion-implanted wafer after bonding (ion implantation separation method: smart).
- ion implantation separation method smart
- a technique called a cutting method is attracting attention.
- an oxide film is formed on at least one of two silicon wafers, and gas ions such as hydrogen ions or rare gas ions are implanted from the upper surface of one silicon wafer (bond wafer),
- An ion implantation layer (also referred to as a microbubble layer or an encapsulation layer) is formed inside the wafer.
- the surface into which the ions are implanted is brought into close contact with the other silicon wafer (base wafer) through an oxide film, and then a heat treatment (peeling heat treatment) is applied to form a microbubble layer as a cleaved surface on one wafer (bond wafer). )
- a heat treatment peeling heat treatment
- This ion implantation separation method is not limited to the case of manufacturing a bonded SOI wafer through an insulating film, but is also applied to the case of manufacturing a bonded wafer by directly bonding two wafers.
- the bond wafer after delamination (peeling wafer) is subjected to reprocessing (refresh processing) including surface treatment such as polishing and etching again, thereby causing a step generated in the unbonded portion, The surface roughness after peeling and the influence of the implanted residual layer are reduced or eliminated, and the wafer can be used repeatedly.
- reprocessing fresh processing
- surface treatment such as polishing and etching again
- Patent Document 3 describes that the polishing margin of the peeled wafer surface is 2 ⁇ m or more, and that the peeled wafer is repeatedly reused as a bond wafer.
- Patent Document 4 describes that polishing of about 5 ⁇ m can be repeated up to 10 times in repeated reuse of a peeled wafer.
- Patent Document 5 describes that the polishing margin of the peeled wafer surface is set to 1 to 5 ⁇ m or more, and the peeled wafer is reprocessed many times.
- the present invention has been made in view of the above-described problems, and suppresses unevenness in the thickness of a marble pattern generated in a thin film when a bonded wafer is manufactured by an ion implantation separation method.
- the object is to produce a high bonded wafer.
- an ion-implanted layer is formed by ion-implanting at least one kind of gas ions of hydrogen ions and rare gas ions on the surface of a bond wafer.
- a part of the bond wafer is peeled off by the ion-implanted layer by applying a heat treatment on the base wafer.
- the bonded wafer manufacturing method for producing a bonded wafer having a thin film before bonding the bond wafer and the base wafer, the thickness of the bond wafer and the base wafer is measured, and the difference between the thicknesses of the two wafers is measured.
- Such a method for manufacturing a bonded wafer can suppress unevenness in the thickness of the thin film and can manufacture a bonded wafer having high film thickness uniformity.
- the heat treatment is preferably performed at 350 ° C. or higher.
- a reclaimed wafer that has been subjected to recycle processing accompanied by thickness reduction is applied to the peeled wafer produced as a by-product when the bonded wafer is produced in the method for producing a bonded wafer.
- This reclaimed wafer can be one that has been subjected to reclaiming with the above-described thickness reduction twice or more, or one that has been subjected to a thickness reduction of 5 ⁇ m or more as the reclaiming with the above-mentioned thickness reduction.
- the present invention can be suitably applied to such a regenerated wafer that tends to cause film thickness unevenness in particular, and a bonded wafer with high film thickness uniformity can be manufactured while reducing costs.
- the bond wafer and the base wafer can be made of a silicon single crystal wafer
- the insulating film can be made of a silicon oxide film
- the thin film can be an SOI layer. In this way, it is possible to manufacture an SOI wafer with high uniformity of the thin film of the SOI layer.
- the thickness of the bond wafer and the base wafer is measured before the bond wafer and the base wafer are bonded, and the difference between the thicknesses of the two wafers is 5 ⁇ m or more.
- a combination of wafers is selected, and heat treatment is performed at 400 ° C. or less, and a part of the bond wafer is peeled off by the ion implantation layer, so that the film thickness unevenness of the thin film can be suppressed and the bonded wafer having high thin film thickness uniformity. Can be manufactured.
- the present invention is not limited to this.
- the regenerated processing with a reduction in thickness is performed on the separation wafer produced as a by-product when the bonded wafer is manufactured.
- the wafer is often used as a bond wafer or a base wafer.
- an unused wafer (a wafer that has not been reprocessed, hereinafter referred to as a prime wafer) may be used as the bond wafer and the base wafer.
- the thickness of a silicon single crystal wafer used as a bond wafer and a base wafer is manufactured with a standard of ⁇ 15 ⁇ m.
- the thickness variation between wafers is accurate to about ⁇ several ⁇ m. Therefore, the use of prime wafers manufactured in the same manufacturing lot is unlikely to cause film thickness unevenness.
- the production lots are different and the median thickness of the wafers is shifted, even between prime wafers, the difference in thickness between both wafers may exceed 5 ⁇ m, resulting in film thickness unevenness. Increases frequency.
- a recycled wafer When a recycled wafer is used as at least one of a bond wafer and a base wafer, the wafer is thinned by a thickness reduction process, so that the possibility that the thickness difference between both wafers exceeds 5 ⁇ m increases.
- a prime wafer is used as one of the bond wafer or the base wafer and a recycled wafer is used as the other, this possibility is very high. Therefore, the frequency of occurrence of film thickness unevenness is also increased.
- the bonded SOI wafer manufacturing conditions at this time are shown below.
- (Oxide film) A 55 nm thermal oxide film is formed on the bond wafer, the base wafer has no oxide film, (Hydrogen ion implantation conditions) Injection energy: 48.7 keV, dose amount: 5 ⁇ 10 16 / cm 2 , (Peeling heat treatment) At 350 ° C. for 4 hours + 500 ° C. for 30 minutes, Ar atmosphere, (Planarization heat treatment) Thickness of SOI layer to about 70 nm by sacrificial oxidation treatment at 1200 ° C for 1 hour in Ar atmosphere (SOI film thickness adjustment)
- a bonded wafer having a thin film on a base wafer for example, an SOI wafer in which an SOI layer is formed on a silicon single crystal wafer via a silicon oxide film can be manufactured.
- a bond wafer 10 and a base wafer 11 are prepared.
- a combination of a bond wafer and a base wafer having a thickness difference of 5 ⁇ m or more is selected from a plurality of wafers whose thicknesses have been measured in advance.
- This selection step may be performed before the step of bonding the bond wafer and the base wafer, and is not particularly limited in the order of execution with respect to other steps before the bonding step.
- the selection step may be performed after the step of forming an ion implantation layer on the bond wafer described below.
- a prime wafer or a recycled wafer can be used for both the bond wafer and the base wafer.
- a prime wafer can be used for one of the bond wafer and the base wafer, and a recycled wafer can be used for the other.
- the reclaimed wafer is a wafer obtained by subjecting the peeled wafer produced as a by-product when the bonded wafer is produced as described above to a rework process accompanied by a reduction in thickness. If the reclaimed wafer is used, the cost can be reduced. Therefore, it is preferable.
- reclaimed processing with thickness reduction was performed twice or more, that is, reclaimed wafers that were reused twice or more, or reclaimed wafers with thickness reduction of 5 ⁇ m or more as reclaimed processing with thickness reduction,
- reclaimed wafers that were reused twice or more or reclaimed wafers with thickness reduction of 5 ⁇ m or more as reclaimed processing with thickness reduction
- the film thickness unevenness of the thin film can be suppressed according to the bonded wafer manufacturing method of the present invention.
- an oxide film 12 to be a buried oxide film 16 is grown on the bond wafer 10 by, for example, thermal oxidation or CVD.
- the oxide film 12 formed at this time may be formed only on the base wafer 11 or may be formed on both wafers. When manufacturing a directly bonded wafer, this oxide film does not need to be formed.
- At least one kind of gas ion of hydrogen ions and rare gas ions is implanted into the bond wafer 10 from above the oxide film 12 by an ion implanter.
- An ion implantation layer 13 is formed.
- the ion implantation acceleration voltage is selected so that the target thickness of the peeled silicon (thin film 15) can be obtained.
- the ion-implanted bond wafer 10 is adhered and bonded to the base wafer 11 so that the implantation surface is in contact.
- the bonded wafer is held at a temperature of 400 ° C. or lower for a predetermined time, and a heat treatment (peeling heat treatment) is performed to generate a microbubble layer in the ion-implanted layer 13 and peel off at the microbubble layer.
- a bonded wafer 14 in which a buried oxide film 16 and a thin film 15 are formed on a base wafer 11 as shown is produced.
- the peeling heat treatment is performed at 400 ° C. or less, even if a combination of the bond wafer 10 and the base wafer 11 in which the difference in thickness between the two wafers is 5 ⁇ m or more is selected, the film thickness unevenness of the thin film 15 after peeling is selected.
- the bonded wafer 14 having a high film thickness uniformity of the thin film 15 can be manufactured.
- the temperature of the peeling heat treatment is preferably 350 ° C. or higher.
- the bonding strength of the wafers closely attached at room temperature can be increased by performing a plasma treatment on the surfaces to be bonded in advance. Then, as shown in FIG. 1 (j), the bonded wafer 14 can be subjected to planarization heat treatment, bonding heat treatment, polishing, or the like to flatten the peeled surface or increase the bonding strength.
- a peeled wafer 17 which is the bond wafer 10 after peeling is by-produced.
- the separation wafer 17 has a step portion that has not been transferred to the base wafer 11 on the outer peripheral portion of the separation surface 18.
- Such reclaimed processing for removing the stepped portion of the peeled wafer 17 can be used as a reclaimed wafer at the time of manufacturing the next bonded wafer.
- the reclaiming process of the separation wafer 17 can be performed as follows, for example.
- the oxide film other than the oxide film on the surface opposite to the peeled surface 18 is removed by cleaning with, for example, an HF aqueous solution.
- the peeled surface is polished to flatten the peeled surface and remove the damage layer caused by ion implantation, as shown in FIG.
- the back surface oxide film 12 is removed by performing HF cleaning such as a normal batch type HF liquid bath immersion method, and the same surface and back surface quality as the prime wafer are obtained.
- HF cleaning such as a normal batch type HF liquid bath immersion method
- Example 1-2 Comparative example 1-3
- a bonded SOI wafer by an ion implantation delamination method is produced, and whether or not there is any unevenness in the thickness of the SOI layer evaluated.
- a prime wafer (775 ⁇ m) was used as the base wafer, and a reclaimed wafer (765 ⁇ m) that had been subjected to regenerated polishing twice was used as the bond wafer.
- the peeling heat treatment conditions were the conditions described in Table 3, and the other production conditions were the same as in the experimental example.
- FIG. 2 shows the results (film thickness map) showing the occurrence of film thickness unevenness.
- Table 3 shows the SOI film thickness range (a value obtained by subtracting the minimum value from the maximum value of the in-plane film thickness), while Comparative Example 1-3 was about 2.0 to 2.2 nm.
- Examples 3 and 4 A bonded SOI wafer was prepared under the same conditions as in Examples 1 and 2 except that the peeling heat treatment was 380 ° C. for 12 hours (Example 3), 350 ° C. for 24 hours (Example 4), and the film thickness of the SOI layer was The presence or absence of unevenness was evaluated. As a result, no film thickness unevenness occurred, and the SOI film thickness range was equivalent to those in Examples 1 and 2.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects.
- a case where a bonded SOI wafer is manufactured through an insulating film is described.
- the present invention can also be applied to a case where a bonded wafer is manufactured by directly bonding two wafers. .
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Abstract
Description
このように熱処理を350℃以上で行うことで、イオン注入層でボンドウェーハの一部を確実に剥離させることができる。
このような、特に膜厚ムラが発生しやすい再生ウェーハを用いる場合に本発明を好適に適用でき、コストを低減しつつ、薄膜の膜厚均一性の高い貼り合わせウェーハを製造できる。
このようにすれば、SOI層の薄膜の膜厚均一性の高いSOIウェーハを製造できる。
一般的に、イオン注入剥離法により貼り合わせSOIウェーハを作製する場合には、コスト削減のため、貼り合わせウェーハを作製する際に副生された剥離ウェーハに減厚を伴う再生加工を行った再生ウェーハをボンドウェーハまたはベースウェーハとして用いることが多い。或いは、ボンドウェーハおよびベースウェーハとして未使用のウェーハ(再生加工を行っていないウェーハ、以下、プライムウェーハと呼ぶ。)を用いる場合もある。
ボンドウェーハおよびベースウェーハとしてプライムウェーハを用いる場合、両ウェーハが異なる製造ロットで製造されたものである場合にSOI層の膜厚ムラの発生頻度が高くなる。ボンドウェーハおよびベースウェーハの少なくとも一方に再生ウェーハを用いる場合には膜厚ムラの発生頻度がより高くなり、また、その再生回数が多いほど発生頻度が増加する傾向がある。そこで、発明者は、プライムウェーハと再生ウェーハを用いた下記の実験を行い、この発生頻度が高くなる傾向について以下のように考察した。
ボンドウェーハおよびベースウェーハとして、表1に示す厚さを有する直径300mm、結晶方位<100>のシリコン単結晶からなる4種類の鏡面研磨ウェーハを用意した。ウェーハ厚は、静電容量式の測定装置を用いてウェーハ全面を測定し、その平均値(小数点以下四捨五入)を採用した。
[貼り合わせSOIウェーハ製造条件]
(酸化膜)ボンドウェーハには55nmの熱酸化膜を形成、ベースウェーハには酸化膜なし、
(水素イオン注入条件)注入エネルギー:48.7keV、ドーズ量:5×1016/cm2、
(剥離熱処理)350℃で4時間+500℃で30分、Ar雰囲気、
(平坦化熱処理)1200℃で1時間、Ar雰囲気
(SOI膜厚調整)犠牲酸化処理によりSOI層を70nm程度まで減厚
ボンドウェーハとベースウェーハの厚さの差が膜厚ムラの発生にどのように関係しているかのメカニズムについては明らかではないが、厚さが異なると剥離熱処理で剥離する際に、剥離領域の固有振動数が異なることに起因するものと推定される。
以上のように、本発明者は、膜厚ムラの発生がボンドウェーハとベースウェーハの厚さの差が大きいことに起因していることを見出し、更に、厚さの差が大きい場合であっても、剥離熱処理を400℃以下で行えば、SOI層の膜厚ムラが発生しないことを見出し、本発明を完成させた。
本発明では、ベースウェーハ上に薄膜を有する貼り合わせウェーハとして、例えば、シリコン単結晶ウェーハ上にシリコン酸化膜を介してSOI層が形成されたSOIウェーハを作製することができる。
次に、図1(d)に示すように、イオン注入したボンドウェーハ10を、注入面が接するように、ベースウェーハ11と密着させて貼り合わせる。
剥離熱処理を350℃以上で行うことで、イオン注入層13でボンドウェーハ10の一部を確実に剥離させることができる。なお、ドーズ量が同一であれば、剥離熱処理の温度が低いほど剥離に必要な時間が長くなる傾向があるので、熱処理時間はドーズ量と剥離熱処理温度を考慮して適宜設定することができる。
そして、図1(j)に示すように、この貼り合わせウェーハ14に、平坦化熱処理、結合熱処理、研磨等を施して、剥離面を平坦化したり、結合強度を高めることもできる。
直径300mm、結晶方位<100>のシリコン単結晶からなる鏡面研磨ウェーハをボンドウェーハおよびベースウェーハとして用いてイオン注入剥離法による貼り合わせSOIウェーハを作製し、SOI層の膜厚ムラの発生の有無を評価した。
このとき実施例1-2、比較例1-3のいずれもベースウェーハとしてはプライムウェーハ(775μm)を用い、ボンドウェーハとしては、再生研磨加工を2回行った再生ウェーハ(765μm)を用いた。
また、剥離熱処理条件は表3に記載された条件とし、その他の製造条件は実験例と同一とした。
剥離熱処理を380℃、12時間(実施例3)、350℃、24時間(実施例4)とした以外は実施例1、2と同一条件で貼り合わせSOIウェーハを作製し、SOI層の膜厚ムラの発生の有無を評価した。
その結果、膜厚ムラは発生せず、SOI膜厚レンジも実施例1、2と同等であった。
例えば、上記では、絶縁膜を介して貼り合わせSOIウェーハを作製する場合について説明しているが、直接2枚のウェーハを貼り合わせて貼り合わせウェーハを作製する場合にも本発明を適用可能である。
Claims (6)
- ボンドウェーハの表面に、水素イオン、希ガスイオンのうち少なくとも一種類のガスイオンをイオン注入してイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面と、ベースウェーハの表面とを直接または絶縁膜を介して貼り合わせた後、熱処理を加えて前記イオン注入層で前記ボンドウェーハの一部を剥離させることにより、前記ベースウェーハ上に薄膜を有する貼り合わせウェーハを作製する貼り合わせウェーハの製造方法において、
前記ボンドウェーハとベースウェーハを貼り合わせる前に、前記ボンドウェーハと前記ベースウェーハの厚さを測定し、両ウェーハの厚さの差が5μm以上である前記ボンドウェーハと前記ベースウェーハとなる組み合わせを選択し、
前記熱処理を400℃以下で行って前記イオン注入層で前記ボンドウェーハの一部を剥離させることを特徴とする貼り合わせウェーハの製造方法。 - 前記熱処理を350℃以上で行うことを特徴とする請求項1に記載された貼り合わせウェーハの製造方法。
- 前記ボンドウェーハおよび/または前記ベースウェーハとして、前記貼り合わせウェーハの製造方法において貼り合わせウェーハを作製する際に副生された剥離ウェーハに、減厚を伴う再生加工を行った再生ウェーハを用いることを特徴とする請求項1又は請求項2に記載された貼り合わせウェーハの製造方法。
- 前記再生ウェーハは、前記減厚を伴う再生加工が2回以上行われたものであることを特徴とする請求項3に記載された貼り合わせウェーハの製造方法。
- 前記再生ウェーハは、前記減厚を伴う再生加工として5μm以上の減厚が行われたものであることを特徴とする請求項3又は請求項4に記載された貼り合わせウェーハの製造方法。
- 前記ボンドウェーハおよび前記ベースウェーハがシリコン単結晶ウェーハからなり、前記絶縁膜がシリコン酸化膜からなり、前記薄膜がSOI層であることを特徴とする請求項1乃至請求項5のいずれか一項に記載された貼り合わせウェーハの製造方法。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JP2001155978A (ja) | 1999-11-29 | 2001-06-08 | Shin Etsu Handotai Co Ltd | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
JP2003347526A (ja) * | 2002-05-02 | 2003-12-05 | Soi Tec Silicon On Insulator Technologies | 材料の二層を剥離する方法 |
JP2006140445A (ja) | 2004-11-09 | 2006-06-01 | Soi Tec Silicon On Insulator Technologies Sa | 複合材料ウェーハの製造方法 |
JP2007149907A (ja) | 2005-11-28 | 2007-06-14 | Sumco Corp | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
JP2008021892A (ja) | 2006-07-14 | 2008-01-31 | Shin Etsu Handotai Co Ltd | 剥離ウェーハを再利用する方法 |
WO2009141954A1 (ja) * | 2008-05-21 | 2009-11-26 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせウェーハ |
JP2013089720A (ja) * | 2011-10-17 | 2013-05-13 | Shin Etsu Handotai Co Ltd | 剥離ウェーハの再生加工方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4839818B2 (ja) * | 2005-12-16 | 2011-12-21 | 信越半導体株式会社 | 貼り合わせ基板の製造方法 |
JP5888286B2 (ja) * | 2013-06-26 | 2016-03-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
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Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JP2001155978A (ja) | 1999-11-29 | 2001-06-08 | Shin Etsu Handotai Co Ltd | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
JP2003347526A (ja) * | 2002-05-02 | 2003-12-05 | Soi Tec Silicon On Insulator Technologies | 材料の二層を剥離する方法 |
JP2006140445A (ja) | 2004-11-09 | 2006-06-01 | Soi Tec Silicon On Insulator Technologies Sa | 複合材料ウェーハの製造方法 |
JP2007149907A (ja) | 2005-11-28 | 2007-06-14 | Sumco Corp | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
JP2008021892A (ja) | 2006-07-14 | 2008-01-31 | Shin Etsu Handotai Co Ltd | 剥離ウェーハを再利用する方法 |
WO2009141954A1 (ja) * | 2008-05-21 | 2009-11-26 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせウェーハ |
JP2013089720A (ja) * | 2011-10-17 | 2013-05-13 | Shin Etsu Handotai Co Ltd | 剥離ウェーハの再生加工方法 |
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