TWI303842B - Method for manufacturing compound material wafers - Google Patents
Method for manufacturing compound material wafers Download PDFInfo
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- TWI303842B TWI303842B TW094129941A TW94129941A TWI303842B TW I303842 B TWI303842 B TW I303842B TW 094129941 A TW094129941 A TW 094129941A TW 94129941 A TW94129941 A TW 94129941A TW I303842 B TWI303842 B TW I303842B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000000463 material Substances 0.000 title claims abstract description 39
- 150000001875 compounds Chemical class 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 235000012431 wafers Nutrition 0.000 title abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 121
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 59
- 238000012545 processing Methods 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 210000001787 dendrite Anatomy 0.000 claims 1
- 230000003287 optical effect Effects 0.000 abstract 1
- 238000012546 transfer Methods 0.000 description 16
- 230000008021 deposition Effects 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 238000009420 retrofitting Methods 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/93—Ternary or quaternary semiconductor comprised of elements from three different groups, e.g. I-III-V
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Chemical Vapour Deposition (AREA)
- Physical Vapour Deposition (AREA)
Description
•1303842 九、發明說明: 發明所屬之技術領域 本發明係關於根據申請專利範圍第1項的前言之化合 物材料晶圓的製造方法。 先前技術 由文件US 2003/0153163已知有運用智慧切削 • (SmartCut)技術將供體基材的材料層轉移至處理基材的方 法。該習知的方法包含藉著層將轉移自彼轉移的初始晶圓 黏合於支樓基材而形成供體基材的步驟。根據us 2003/0153163,此供體晶圓之形成將有利於轉移昂貴材料 層,因為除非已經消耗掉該初始晶圓整個厚度不然就可 自同一最初的初始晶圓重複進行數次的轉移操作。 但是該習知方法具有下列問題。由於該供體基材係由 兩個黏合的晶圓組成,所以其厚度,特別是針對最初幾次 •的轉移’經常都比標準方法中,例如在絕緣體晶圓上製造 矽的智慧切削技術方法中,的供體晶圓之厚度大許多。因 此,必須特地改造該轉移方法的期間用於處理並且支撐該 供體晶圓的設備以增加重量及厚度,或必須特地降低該支 樓基材的厚度。但是,兩種可行的方式都f要非常昂貴的 改造步驟。此外,在該製造方法的期間,該供體晶圓的厚 度一直變化,變化的程度取決於進行的轉移次數。結果加 工及處理設備必須經特殊地設計以因應變化的條件。因此 該没備必須經特殊地設計進而變得又更昂貴 1303842 、 發明内容 • 因此,本發明的目的在於提供可克服此技藝現況的問 題使知化合物材料晶圓可使用標準晶圓加工設備製造之化 合物材料晶圓的製造方法。 本目的得利用依據申請專利範圍第丨項之化合物材料 曰曰圓的製造方法達到。因此,本發明的方法包含下列步驟: # 叻提供初始供體基材,b)在該初始供體基材中形成預定 分裂區,c)將該初始供體基材黏接於處理基材,以及d)由 預定分裂區之處分開該供體基材,藉以將該初始供體基材 上的層轉移到該處理基材上而形成化合物材料晶圓,而且 其特徵為e)經分開步驟之後在該供體基材其餘部分上沈 積一層以至少部分地補償該初始供體基材的厚度,及以 含該沈積層的供體基材充當初始供體基材再使用於步驟a) 中。 _ 用於本發明方法的供體基材比用於此技藝方法現況 中的供體基材更薄,這是因為本發明方法的供體基材並未 黏合於額外的支撐基材。再者,由於沈積層的關係,該供 體基材的厚度不會變化太大,可使用標準晶圓加工設備, 所以不需要耗費時間及昂貴的改造或特殊處理設備。因此 實現本發明的方法比先前技藝的方法更加便宜。 在再使用該供體基材其餘部分之前,可在將黏接於該 處理基材之供體基材其餘部分的表面上進行額外的修復步 驟。此修復舉例來說可藉由研磨而進行。 6 1303842 有利地在進行該沈積步冑e)之前先重複進行步驟a) 至d)至少兩次,其中在重複步驟勾中以該供體基材分開的 其餘部分再使用作為初始供體基材。由於較少步驟對應於 較快且因此較不貴的製造方法,所以在沈積之前該方法的 重複部分將進一步助於使該方法最適化。 較佳地,重複步驟a)至d)直到該初始供體基材達到預 定的最小厚度為止°重複次數的上限可藉由該基材的性 馨質’例如機械強度’開始劣化之供體基材其餘部分的厚度 而決定,或與可能需要某特定最小厚度才能適當地發生功 效之處理設備的性質有關。由於重複進行的關係,當該化 合物材料晶圓的品質及生產量可維持在高標時整個方法將 可進一步最適化。 根據其中之一較佳具體例,可以均質為晶的方式沈積 步驟e)中的層。本發明的方法對於昂貴的供體基材特別有 利’而其通常為結晶性材料。藉著以均質蠢晶的方式再生 _長該供體基材達初始厚度或超越,若該㈣基材可 的次數超過必須消耗該初始供體基材的厚度之次數,那麼 事實上該方法將變得與供供體基材的可取得性無關。 在本文中,均質磊晶表示相同材料的沈積層與該初始 供體基材的材料具有相同的結晶性質。 較佳地在步驟e)中可使用金屬有機化學氣相沈積 (MOCVD)法、氫化物氣相蠢晶(HvpE)法或分子束蠢晶 (MBE)法而提供該均質磊晶層’藉以達到與該初始供體基 材相比時,該均質蠢晶層中有經改善的位錯密度之目的^ 7 1303842 特別是小於每平方公分1 X 1 07的位錯密度’特別是小於每 平方公分1 X 106的位錯密度。在生長的期間位錯傾向阻斷 . 於特定量下,使得額外長成的材料呈現較低的位錯密度。 因此,該供體基材材料的品質將變得更好,所以與市面上 藉由標準供體基材可達成的轉移層相比,該轉移層的品質 亦將變得更佳。 有利地步驟e)可包含將該層提供於該供體基材其餘部 φ 分的表面側上,而其相對於發生分開之處的表面側。若使 用極性供體基材,表示該基材的兩個主要表面具有不同的 性質,事實上通常都是其中之一表面的磊晶生長可控制良 好’然而另一個表面則非如此。該材料化合物晶圓的轉移 層之自由面應該對應於極性能使其他磊晶層制約生長的表 面,而在進一步的加工步驟中可能需要該磊晶層以建構微 電子或光電元件。結果黏接於該處理基材表面的轉移層表 面將具有第二種極性。因此在發生分開之處的供體基材其 籲餘部分的表面具有磊晶生長並未控制的那麼好之極性。因 此額外層的沈積最好在相反側進行,其中將會發生如此的 制約均質蠢晶生長,而使得沈積層的品質良好。 較佳地在進行步驟e)之前,可利用保護層,特別是使 用氧化物及/或氮化物層,提供發生分開之處的表面側。此 保護層可有利地防止該供體基材其餘部分受到像是金屬或 粒子的污染,特別是在該晶圓目反側的層沈積期間。此保 護作用具有改善或維持該化合物材料晶圓的品質之功能。 有利地’該方法在再使用含該層的供體基材作為初始 8 1303842 供體基材之前可包含另一個移除該保護層的步驟。最後該 移除步驟可伴隨額外的研磨或清潔步驟。因此,將該供體 基材的保護面側黏接於處理基材時,再使用供體基材的表 面性質將使得黏合的目的可達成而且其中達到黏合之處具 有高表面品質。 有利地,可在該層的沈積之前先研磨及/或清潔其上在 步驟e)中提供該層之供體基材其餘部分的表面側。這將改 _ 善沈積層的品質,而其於沈積層為均質蠢晶層時特別令人 感到有興趣,反過來說在該製造方法的後續階段期間將以 其作為轉移層。 該方法特別有利於該供體基材為下列群組其中之一 的情況:氮化鎵(GaN)、碳化矽(SiC)、鍺(Ge)、氮化鋁(AiN) 或鑽石。這些基材在電子應用方面扮演著重要的角色而且 在合理的價格下難以獲得良好的品質。與整塊材料本身相 比,藉著使用上述利用此類材料的方法將可能達到比較便 _ 宜之品質良好的材料化合物晶圓。 較佳地所用的處理基材為单晶型或多晶型材料,特別 是下列群組其中之一 ··砷化鎵(GaAs)、氧化鋅(Zn0)、碳化 矽(SiC)或氮化鋁(A1N)。較佳為使用具有類似於該供體基材 材料的熱膨脹係數之處理基材,而進一步改善該材料化合 物晶圓的品質。為了進一步的成本降低,與單晶型材料相 比使用多晶型材料可能較為有利。在更一般性的情況中, 該處理基材也可由石夕(Si)、玻璃或陶瓷材料形成。 根據一個變體,可供給該處理基材絕緣層,特別是二 9 •1303842 圓10及該初始基材的其餘部分9 人, 在進一步加工該材料化 口物晶圓10之前可能會先受到最 又j玻終的表面處理,像是例如 研磨及/或清潔。
現在該供體基材的其餘部分9(第lf圖)可再使用作為 初始供體基材丨並且利用第la圖中舉例說明的步驟再啟動 該方法或者可沈積層’而其將參照第圖在以下加以說 明。最後在再使用之前,在發生分開之處的表面^可藉著, 舉例來說’在下列第卜及ld圖所示的植人及黏合步驟之 前先研磨而修復。此供體基材的其餘部分9可重複再使用 的情況可進仃數次’例如若咸認為每次層轉移及修復導致 約5微米厚度的移除,而且自供體基材i整體移除約5〇微 米導致該基材的脆化就表㈣除太多而無法保持適於應用 的轉移層品質的話,那麼將可達10次。 因此,一旦已經達到該供體基材的其餘部分9之最小 厚度或該Ss設備要保證該方法有發揮良好效用所需的最 小厚度’该方法就進行第lg圖中舉例說明的步驟,換言之 將層12沈積於該供體基材的其餘部分9上。該沈積層12 的厚度可至少部分地補償該初始供體基材丨的厚度,使得 此經修復的供體基材14可再使用作為初始供體基材1,舉 例說明於第1 a圖中。 根據一個變體,舉例說明於第2a圖中,該沈積層12, 係由可快速地沈積於相對於其上發生分開的表面丨丨之該基 材其餘部分9的表面側! 5上之材料構成。因此,根據該變 體,要強調的是事實上該供體基材的其餘部分9係快速地 12 1303842 回復到足敷進—步再使用的厚度。如此該沈積層12,的材料 就不-定要與該初始供體基材9的材料相同。然而,若已 經將該層12’的材料選擇為與該供體基材9的材料相同那 麼就可選擇生長條件使得生長速度最適化。在此例中該額 外層12’的結晶品質可能不敷供後續作為轉移層6之用。在 此例中,一旦該初始供體基材丨已經完全消耗掉,製程中 就必須再導入新的供體基材晶圓1。
根據該變體,舉例說明於第沘圖中,該沈積層Μ,,係 由與該供體基材的其餘部分9相同的材料構成而且,附帶 地,係以均質磊晶的方式生長,使得該層12,,的結晶品質至 少可與基材其餘部分9的品質相容。層12”可沈積在表面 11或表面15上。在此例中,製程中不需導入新的供體基材 1,而且該沈積層12”可在後續作為轉移層6。使用 MOCVD、HVPE或MBE方法,甚至可得到結晶品質比該供 體基材1的初始品質更好的層12”。特別是可達到小於每平 方公分1 X 107的位錯密度,如果該初始供體基材的位錯密 度經常都大於此值的話。 在第2a圖的例子中經修復的供體基材14與處理基材 2之間的黏接將經由表面11而發生。在第2 b圖的例子中可 經由兩個表面發生黏接。 第3圖舉例說明本發明製造方法的第二個具體例,其 中藉由第3a至3c圖中舉例說明的步驟代替第ig圖中舉例 說明的步驟。具有與第1圖中使用的相同參考編號之元件 及特徵可相對應,因此不再詳細解釋,但是將它們的說明 13 1303842
面;8··供體處理化合物; 主要元件之符號說明 L初始供體基材; 4··預定分裂區;5. 6..轉移層; 7··處理基材的主要表面 9··供體基材的其餘部分;1〇•化合物材料晶圓; 11··發生分開之處的表面;12、12,、12,,··沈積層; 13··沈積層的厚度;ι4.經修復的供體基材; _ 15··基材其餘部分的表面侧;16··額外層的表面; 30..保護層 17
Claims (1)
1303842 年;7月修(受:)正本 y (2008年7月修7Π 。十、申請專利範圍: 1 · 一種化合物材料晶圓之製造方法,其包含下列步驟·· a)提供初始供體基材(1), ' b)在該初始供體基材(1)中形成預定分裂區(4), , c)將該初始供體基材(1)黏接於處理基材(2),以及 ^ d)由預定分裂區(4)之處分開該供體基材(1),藉以將該 初始供體基材(1)上的一層轉移到該處理基材(幻上 而形成化合物材料晶圓(1 〇),而且 _ e)經分開步驟之後在該供體基材(1)的其餘部分(9)上沈 積一層(12)以至少部分地補償該初始供體基材(1)的 厚度, f)以含該沈積層(12)的供體基材(1)充當初始供體基材 (1)再使用於步驟a)中,及 其特徵為 步驟e)包含|該層(12)設置於該供體基材其餘部分⑺的 表面側(15)上,而其相對於發生分開之處的表面側⑴)。 2.如申請專利範圍帛1項之方法’其中該方法包含在進行 步驟e)之前重複進行步驟a)至d)至少兩次,#中在重複 步驟a)巾再使用經分開的供録材其餘部㈣為初始供 體基材(1)。 i如中請專利範圍帛2項之方法’其中重複進行步驟a)至 d) 直到該初始供體基材(1)達到預定的最小厚声 4.如申請專利範圍第…項中任一 又:。 、山 ,丫仕項之方法,其中步驟 e) 中的層(12)係以均質磊晶的方式沈積。 18 1303842 , (2008年7月修正) 5·如申請專利範圍第4 貝之方法,其中在步驟e)中使用 、VD HVPE或MBE法提供該均質蠢日日日層(12),藉以 達L、該初始供體基材相比時,該均質蟲晶層⑽中有 經改善的位錯密度之目的,特別是小於每平方公分i x 勺位錯4度,特別是小於每平方公分1 x 1G6的位錯 密度。 6. 如申:專利範圍第i項之方法,其中該方法包含在步驟 6)之則先在發生分開之處的表面側(11)設置保護層 (3〇),特別是使用氧化物及/或氮化物。 曰 7. 如申請專利ϋ圍f 6項之方法,其中該方法進—步包含 在再使用含該層(12)的供體基材⑴作為初始供體基材⑴ 之前移除該保護層(30)的步驟。 8. 如申請專利範圍帛μ之方法,其中該方法進—步包含 研磨及/或清潔將在步驟e)中於其上設置該層之供體基 材其餘部分(9)的表面側(11、15)之步驟。 9 ·如申請專利範圍第彳^ 囷罘1項之方法,其中該供體基材(1)為下 列群組其中之一:GaN、Sic、Ge、A1N或鑽石。 1〇.如申請專利範圍第w之方法,其中該處理基材⑺為單 晶型或多晶型材料’特別是下列群組其中之一:si、 GaAs、ZnO、SiC 或 A1N 〇 11.如申請專利範圍第i項之方法,其中該處理基材⑺為玻 璃或陶瓷材料。 12•如申請專利範圍第之方法,其中該方法在步驟c)之 珂進一步包含在要黏接於該供體基材(1)之處理基材(2) 19 1303842 - (2008年7月修正) • 的表面(7)上設置絕緣層,特別是Si02或Si3N4或傳導層。
20 1303842
第2a圖 第2b圖 第3a圖
11
第3b圖
第3c圖
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CN101221895B (zh) | 2014-04-23 |
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ATE420461T1 (de) | 2009-01-15 |
CN100426459C (zh) | 2008-10-15 |
TW200824037A (en) | 2008-06-01 |
KR100746182B1 (ko) | 2007-08-03 |
KR20060052446A (ko) | 2006-05-19 |
US7851330B2 (en) | 2010-12-14 |
CN101221895A (zh) | 2008-07-16 |
DE602004018951D1 (de) | 2009-02-26 |
US20090191719A1 (en) | 2009-07-30 |
EP1667223B1 (en) | 2009-01-07 |
JP2006140445A (ja) | 2006-06-01 |
CN1790620A (zh) | 2006-06-21 |
JP4489671B2 (ja) | 2010-06-23 |
EP1962340A3 (en) | 2009-12-23 |
SG122972A1 (en) | 2006-06-29 |
US20110049528A1 (en) | 2011-03-03 |
US20060099776A1 (en) | 2006-05-11 |
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