JP2005531142A - 縦型ｎｒｏｍ - Google Patents

縦型ｎｒｏｍ Download PDF

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Publication number
JP2005531142A
JP2005531142A JP2004515673A JP2004515673A JP2005531142A JP 2005531142 A JP2005531142 A JP 2005531142A JP 2004515673 A JP2004515673 A JP 2004515673A JP 2004515673 A JP2004515673 A JP 2004515673A JP 2005531142 A JP2005531142 A JP 2005531142A
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Japan
Prior art keywords
source
region
drain region
mosfet
drain
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Pending
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JP2004515673A
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Japanese (ja)
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JP2005531142A5 (enExample
Inventor
フォーブス、レオナルド
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Micron Technology Inc
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Micron Technology Inc
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Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of JP2005531142A publication Critical patent/JP2005531142A/ja
Publication of JP2005531142A5 publication Critical patent/JP2005531142A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2004515673A 2002-06-21 2003-05-08 縦型ｎｒｏｍ Pending JP2005531142A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/177,208 US6853587B2 (en) 2002-06-21 2002-06-21 Vertical NROM having a storage density of 1 bit per 1F2
PCT/US2003/014497 WO2004001856A1 (en) 2002-06-21 2003-05-08 Vertical nrom

Publications (2)

Publication Number Publication Date
JP2005531142A true JP2005531142A (ja) 2005-10-13
JP2005531142A5 JP2005531142A5 (enExample) 2006-06-15

Family

ID=29734319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004515673A Pending JP2005531142A (ja) 2002-06-21 2003-05-08 縦型ｎｒｏｍ

Country Status (7)

Country Link
US (4) US6853587B2 (enExample)
EP (1) EP1518278A1 (enExample)
JP (1) JP2005531142A (enExample)
KR (1) KR100698977B1 (enExample)
CN (1) CN1672265A (enExample)
AU (1) AU2003228940A1 (enExample)
WO (1) WO2004001856A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
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JP2006114921A (ja) * 2004-10-08 2006-04-27 Silicon Storage Technology Inc Ｎｒｏｍデバイス及びその製造方法
JP2008141196A (ja) * 2006-11-30 2008-06-19 Dongbu Hitek Co Ltd フラッシュメモリ素子
JP2011514013A (ja) * 2008-03-13 2011-04-28 マイクロン テクノロジー， インク． 単一の導電柱への一対のメモリセルストリングを備えたメモリアレイ
JP2011211223A (ja) * 2004-03-22 2011-10-20 Hynix Semiconductor Inc 電荷トラップを有するゲート誘電体を含む揮発性メモリ及びその製造方法

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