TWI285414B - Non-volatile memory and manufacturing method and operating method thereof - Google Patents

Abstract

A non-volatile memory unit includes a substrate, a conductive layer, a charge storage layer, a first doped regions, two second doped regions, a first bit line and a second bit line. Wherein, there is a trench in the substrate, the conductive layer is disposed in the substrate and filled the trench. The charge storage layer is disposed between the conductive layer and the substrate. The first doped region is disposed in the substrate below the trench, and the second doped regions are disposed in the substrate on the two sides of the trench respectively. Plural control gates are located above the select gates and aligned in parallel and extend in a second direction. The first bit line and the second bit line are disposed on the substrate and electrically connected to the two second doped regions respectively and parallel to each other.

Description

Non-Zenary memory

[Technical Field] The present invention relates to a semiconductor device, a method of fabricating the same, and a method of operating the same, and more particularly to a nonvolatile memory and a method of fabricating and operating the same. [Prior Art] ----- w ^ a j τ soil less, δ δ δ 匕 匕 」 ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” It will not disappear after the power, so it has become a memory component widely used in personal computer 3 electronic equipment. A typical electrically erasable and programmable read-only memory system uses a doped multi-turn 矽 to create a floating gate and a control gate (c〇ntr Gate). When the memory is programmed (Pr〇gram), the injected floating gate # electrons are evenly distributed throughout the polysilicon floating gate layer. However, when there is a defect in the penetrating layer under the polycrystalline slab floating layer, it is easy to cause leakage current of the component and affect the reliability of the component. 3 “'In order to solve the problem that the eraser can read the memory device, the drain arm=set the second material is to use a charge storage fine.” ^曰^ Placement pole' The material of the charge storage layer is, for example, nitride. Xi. ^ The charge storage layer usually has a layer of oxidized oxide on the upper and lower sides to form a (Sta^cked^^ /, EEPROM il 矽 矽 矽 / 矽 矽 / 矽 (SONOS) memory with this stack of gate structure Apricot application" 4: On the control pole and source/drain region of this tl piece for stylization 5 8 1285411, 99twf.doc/g, when the channel area is close to the secret zone, hot electrons will be generated. In the human charge storage layer, since the nitrogen cut has a hostile electron, @ this, the electrons in the charge storage layer are not evenly distributed throughout the charge storage layer, but are collected in a local area of the charge storage layer. Since the electrons injected into the electrical storage layer only hit the local _ domain, the sensitivity of the defects in the oxide layer is small. The leakage current of the component is less likely to occur. However, the stacked gate is located on the surface of the substrate. The planar SONOs memory has the problem that it cannot be programmed/read at the same time, and the same problem also occurs in the vertical structure SONOS memory proposed by Micro Technology in U.S. Patent No. 8,535,78. In view of this, this The purpose of the present invention is to provide a non-volatile memory unit that can simultaneously program/read/erase two memory cells of a memory unit. Another object of the present invention is to provide a non-volatile The memory matrix J has self-aligned word lines, source lines and drain regions. It is still another object of the present invention to provide a method for fabricating a non-volatile memory array, which can simplify the process. A further object is to provide a method for operating a non-volatile memory, which can operate the memory unit more easily. The present invention provides a non-volatile memory unit comprising a substrate, an i-conductor layer, an electrical storage layer, a first doped region, two second doped regions, a strip first wire and a second wire. wherein the substrate has a trench, and the conductor layer is disposed in the trench and is in the trench The direction 12854 layer is disposed between the conductor layer and the substrate. The first-changing region, the bottom portion, the second=one: and the second second impurity region are respectively disposed on the two sides of the trench and electrically connected to the second wire Parallel configuration On the substrate, the sub-system is connected to the layer, and the second and second wires are stored in the preferred embodiment. a money plug, disposed on the substrate, the second doped region and the first wire on the other side, and the trench and the doped region and the second wire. The memory is described in the preferred embodiment as described above. The material of the bulk layer is, for example, doped polycrystalline stone. Memory trt is described in the preferred embodiment. In the above non-volatile, the material of the charge storage layer includes tantalum nitride. In a preferred embodiment, the non-volatile layer g is further provided with a first dielectric layer disposed in the charge storage; The material of the non-volatile first-dielectric layer includes oxygen cutting. In the preferred embodiment of the memory, in the non-volatile layer 7L, the second dielectric layer is further included in the charge storage memory: a preferred one of the present month The material f of the second dielectric layer in the above-mentioned non-volatile first embodiment includes oxygen cutting. According to the present invention, in the above non-volatile 12854 ^^99 twf.doc/g memory unit, the materials of these conductive plugs include polycrystalline stone. According to a preferred embodiment of the present invention, in the above memory unit, the material of the first wire and the second wires comprises gold-tungsten tungsten. A unit of work, a body array, including a base, a majority of memory cells and a number of isolation structures. Among them, the substrate

Several ditches' These ditches are arranged in parallel and are oriented in the direction of the column; ^ Several isolation structures are placed in the substrate to isolate these memory cells. 5 number = memory cell, composed of a plurality of memory cells, each memory bar word line, a layer of charge storage layer, a first doped region, a Zeng ΐ ΐ, a third doped region, Article - wire, a second wire. Among them, the 'word line is arranged in these trenches', and the ί layer is matched with the !! The first first doped regions under the charge reservoir are disposed for the corresponding ones. a second doped region and a plurality of memory cells of the column

The miscellaneous regions are staggered, and the bifurcations 'second doped regions and the third doped lines and the second green guides' are disposed in the bases on both sides of the ditch. The first-conductor is electrically connected to the substrate, is disposed on the substrate, extends in the direction of the row, and is disposed on the substrate, one of the region and the third doped region. The first wire included in the third wire element is connected to the first doped region. Among them, the two memorandum and the third doped regions of the same-line memory list are staggered and adjacent one. The second doping region or the third doping region is shared by the preferred embodiment of the present invention as described above in the non-volatile 12854 r499twfdoc/g. The 'hidden body array' further includes a plurality of conductive plugs disposed on the substrate, . And: connecting the first doped region and the first thyristor, and the third doped region /, attacking the second wires and the first doping and the third wires. According to a preferred embodiment of the present invention, in the above non-volatile zfe body array, the '9-small structure includes a shallow trench isolation structure. According to the preferred embodiment of the present invention, in the above-mentioned body array, a plurality of first dielectric layers are further included, and between the two electrical storage layers and the surface of the trench. According to a preferred embodiment of the present invention, in the non-volatile memory array, a plurality of second dielectric layers are further disposed between the two charge storage layers and the word line. The invention proposes a method for manufacturing a non-volatile memory. Second: 底 bottom row: a plurality of isolation structures are formed in the substrate, and the isolation structures are arranged in a thousand ridges and extend in a sub-first direction. Then, the secret = solid trenches - these trenches are arranged in parallel 'and in the second; the upward extension: its wide-direction intersects with the younger direction. New's underneath these gullies, the bottom of the i-doped region, and the bases on both sides of the trenches are 幵 成 个 个 个 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及; = : Brother : Down 'to form a majority of the surface of the substrate in these trenches to form a multi-solid storage layer filled with these trenches on the substrate, forming a plurality of first-wires and a plurality of strips on the substrate. After that, the electrical lines connecting the second doped regions and the third lines respectively and the second wires are arranged in parallel, and the third side is replaced by the first side == 弟一导1285411 99twfdoc/g according to the present invention. In a preferred embodiment, the method for manufacturing a non-volatile memory device further includes forming a plurality of conductive plugs on the substrate for respectively connecting the second doped regions and the first conductive lines, and; These second doping regions are associated with these second wires. In accordance with a preferred embodiment of the present invention, in the method of fabricating the non-volatile memory described above, the method of forming the first doped regions, the second doped regions, and the third doped regions includes Ion implantation. According to a preferred embodiment of the present invention, in the method of fabricating the non-volatile memory, a first dielectric layer is formed between the underlying charge storage layer and the bottom. According to a preferred embodiment of the present invention, in the method for fabricating the non-volatile memory, a second dielectric layer is formed between the openings of the charge storage layers. In accordance with a preferred embodiment of the present invention, in the method of fabricating the non-volatile memory, the method of forming the word lines first forms a layer of conductive material on the substrate and fills the trenches. Then, move & layers of conductor material formed outside of these trenches. According to a preferred embodiment of the present invention, in the above method of manufacturing a non-volatile memory, a method of removing a layer of a conductive material formed outside the trenches includes a chemical mechanical polishing method. The invention provides a method for operating a non-volatile memory, which is suitable for a memory cell array arranged in rows/columns. The memory cell array is composed of a plurality of memory cells, each memory cell comprising a word line, arranged in a a ditch in the base and extending in the ditch, and the 12854 〇 〇 记忆 memory unit, a 屙 Thunder — - _ _ / storage layer connected to the same column are arranged in the word line and the base Between, the same-column's == ditch! The second and second respectively electrically connected to the second doping extension, the body single 亓妓田一加~A miscellaneous, and the adjacent two memory cells "7 A彳H hetero 11 or the third doped region, and each memory contains the second memory cell of the first memory cell located on both sides of each character line, and the non-winged dragon (four) is the material: ° - The guide is known as the first year of the selected first memory cell: guide, ^ plus = a voltage 'in the first miscellaneous region of the selected first memory cell Shikoudi a voltage' in the selected A memory cell is applied with a third voltage, wherein the first voltage is greater than the second voltage to program the first Above the cell, the third voltage is greater than the threshold voltage of the memory cell; and "the second voltage is applied to the first wire corresponding to the selected first memory cell, and the first doping of the first memory cell of the remote cell The first voltage is applied to the region, and a third voltage is applied to the word line of the remote cell to program the lower bit of the first memory cell. According to a preferred embodiment of the present invention, In the above method for operating a non-volatile memory, the method includes: applying a seventh voltage to a second wire corresponding to the selected second memory cell during the stylizing operation, in the _th of the selected second memory cell Applying an eighth voltage to the inter-cell, applying a ninth voltage to the word line of the selected second memory cell, wherein the seventh voltage is greater than the eighth voltage to program the second memory cell 11 1285414 '99twf.doc/g The upper voltage, the voltage of the ninth voltage is greater than the threshold voltage of the memory unit; and β applies an eighth voltage to the second wire corresponding to the selected second memory cell, and applies the seventh voltage to the first doped region of the selected second memory cell In the second S remembrance of the election The ninth voltage is applied to the word line of the cell to program the lower bit of the second memory cell. According to a preferred embodiment of the present invention, in the method for operating the non-volatile memory, the method includes: When reading the upper cell of the second memory cell, the second wire applied to the second memory cell of the selected second memory cell applies a tenth voltage to the selected second memory cell, and the selected second memory cell The word line is the voltage of the brother 12, wherein the tenth voltage is less than the tenth voltage, and the tenth voltage is greater than the threshold voltage of the critical memory cell before the second memory cell is not programmed; and; 5 取 弟 一 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 自己 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二Apply the twelfth voltage. In the method of operating a memory according to a preferred embodiment of the present invention, the method includes: in the above non-volatile reading of the first memory cell Corresponding first-wire application fourth plant applies a fifth voltage to the selected first memory cell first-doped region, and applies a sixth voltage to the selected first memory cell, wherein the fourth voltage, = first memory cell The word line is not programmed to describe the voltage, and the sixth voltage is greater than the first memory cell.

12 12854 li^twf.doc/g The threshold voltage after characterization; and when reading the bit below the first-memory cell, the fifth voltage is applied to the selected first (four) Γ~ wire to the selected first-memory The fourth voltage is applied to the cell, and the /th pen is applied to the selected first-memory_word line. According to a preferred embodiment of the present invention, in the above non-volatile: memory=operation method, including the word line in the selected memory unit when performing the erase operation Apply two

^四电堡' where the thirteenth voltage is greater than the fourteenth voltage to be erased by the F_N tunneling effect. = In the present invention, the non-mechanical record structure, because there are separate two = 3, at the same time, the two memory cells in the same memory cell are privateized/elected/erased. The manufacturing method of the non-volatile memory of the invention of Luo Bai Er Bu 2 can form a standard word line, a source line and a drain area, which can effectively simplify the process. On the other hand, the method of operating the non-volatile memory of the present invention allows the voltage to be applied to the separated bit lines to more easily operate the L. In order to make the above and other objects, features and advantages of the present invention more obvious, the following is a detailed description, and in conjunction with the closed type, the detailed description is as follows, and the following is a description of the present invention. A perspective view of a manufacturing process for a non-volatile hexanide according to an embodiment of the present invention. 13 12 8 3 4 l· 499twf.d〇c/g 12 8 3 4 l· 499twf.d〇c/g

Referring to Figure 1A, a substrate is provided in which a substrate, such as ochre, ', forms a plurality of isolation structures 102 in the substrate. The isolation structure 102 is, for example, a shallow trench isolation structure, and the material is, for example, an oxygen isolation structure H) 2 is arranged in parallel, and the direction of the 'X direction of the χ γ 平 χ 例如 例如 is, for example, the direction of the row in the memory array, the direction of γ For example, the direction of the columns in the memory array. The isolation structure 1G2 (4) is formed by sequentially forming a recording layer (tree), a hard mask layer (not shown), and a patterned mask layer (not shown) on the substrate HK), and then patterning = The curtain layer is the mask "to the hard mask layer and the pad oxide layer - after a dry moment to make the private Ik, remove the patterned mask layer. Next, a portion of the substrate is removed by using the patterned ruthenium oxide layer and the hard mask layer as a mask to form a plurality of trenches (not shown). Thereafter, a spacer layer is formed on the substrate (10) to fill the trenches, and the hard mask layer is used as a polishing stop layer, and a chemical mechanical polishing process is performed to remove a portion of the spacer material layer to form the isolation structure 102. Following this, the pad oxide layer and the hard mask layer are removed. Next, a well region 1〇4 is formed in the substrate 100, such as a p-type well region. The formation method of the P-type well region is formed, for example, by using boron as a dopant to perform an ion implantation process. In addition, after forming the well region 104, a tempering process can be performed to repair the lattice defects caused to the substrate 100 during ion implantation. Then, please refer to Fig. 1B' to form trenches in the substrate 1〇〇, which are arranged in parallel and extend in the direction of γ. For example, the method of forming the gully 1 〇 6 is to form a patterned mask on the substrate 100 (not shown), and then use the patterned mask layer as a mask to perform 14 128541 ^ 799 twf. 〇c/g A process 'subsequently removes the patterned mask layer to form. A doping process is performed for the substrate 100, for example, an ion implantation process for forming a doped region 110 on the substrate of the trench 106. The swap area should be fr the base area of the base 100. 》# 108 and the noisy area 11〇 are, for example, n-type doping numbers (such as material F in the m: Λ direction number, can be divided into the second two π 1 and 110_3) and the second η (Figure 1Β

More than: area 110·2), η is an integer greater than or equal to 1. Referring to FIG. 1C, the surface shape 112' of the substrate 100 in the trench 106 is, for example, a dielectric layer U2a and a charge storage layer 112b. Composed of. The method for forming the composite layer 112 is, for example, a material for forming the dielectric layer U2a, the charge storage layer 112b, and the dielectric layer 112a, such as yttrium oxide, by a method such as chemical vapor deposition or thermal oxidation. law. The material of the charge storage layer (4) is a nitriding second or a doped polycrystalline second, and the formation method is, for example, a chemical vapor phase.

, the accumulation method. The material of the tantalum layer 112c is, for example, an oxidized stone, and a forming method is, for example, a rhodium chemical vapor deposition method. Then, a word line 114 filling the trench 1〇6 is formed on the substrate 100. The material of the word line 114 is, for example, doped polycrystalline stone, and the forming method is, for example, first, in the presence of field doping, _chemical gas. The phase deposition method forms a layer of doped polysilicon material (not shown) on the substrate 100 and fills the trenches 1〇6. Then, the layer of the modified polycrystalline stone material other than the trench 106 is removed. The method for removing the doped poly (tetra) layer other than the trench 1 〇 6 is, for example, using the substrate 1 〇〇 as the polishing stop layer 'by chemical mechanical polishing to remove 12854 m99 twfd 〇c/g other than the trench 1 〇 6 The polycrystalline stone sealing layer and the composite layer 112 are doped. Next, a bit line m is formed on the substrate 1A with reference to FIG. 1D. The bit line m is electrically connected and 1H) (as shown in Figure m, the doped region is purchased and the u-bit = doped region is connected to the doped region of the second n-th (10). (4) The bit line field 118 is left over, Wherein the 'bit line 116 and the bit line 118 and the doping: the way of the extension' are, for example, the second η 1 connection through the conductive plug 12G: the doped regions i _ and _ 10_3 in the graph m) Connecting with the bit ==, and electrically connecting the doped region in the second figure ω through the conductive plug 120 to the bit line 118 is electrically connected = 1010 (so that the above-described formed bit line 118 can be formed, Forming a dielectric layer (not shown) over the substrate, and placing the germanium line 118, the bit line 120, and the conductive plug

If yes: into this dielectric layer. The material J of the bit line 118 and the bit line 120 is, for example, a metal crane, and the material of the conductive plug 122 is, for example, polycrystalline. In another embodiment, the bit line 118 and the bit line 12g are formed by, for example, forming a conductive plug S 122 and then forming a 2-bit 7G line 118 and a bit line 120. The conductive plug 122 is formed by, for example, forming a patterned mask layer on the substrate 100, and then using a patterned mask layer as a mask to perform a dry process on the dielectric layer covering the substrate to define Conductive plug opening (not shown in green). Subsequently, the patterned mask layer is removed. Then, the deposition process is formed to form a layer of conductive material, and the conductive plug opening is filled, and then a back-cut process is performed to form a conductive plug 12212. The method for forming the bit line 118 and the bit line 12A is, for example, sequentially forming another layer of a conductor material layer (indicated) and a patterned mask layer (not shown) on the dielectric layer, and then patterning The mask layer is a mask, and the conductor material layer is formed by a dry-process. Subsequently, the mask layer was moved. μ In the above-described method for manufacturing a non-volatile memory, the self-alignment 108, the word line 114, and the bit lines 116 and 118 can be formed, which can effectively simplify the manufacturing process and speed up the production. Outside of the sputum, the non-volatile memory formed has a vertical memory cell structure and is a non-volatile memory stored in a single memory cell. The following describes the non-volatile memory structure of the present invention. 2 is a perspective view of a non-volatile memory in accordance with an embodiment of the present invention. Referring to FIG. 2, the non-volatile memory array of the present invention includes a substrate 100, an isolation structure 102, and a memory cell line 122. A well region 104 has been formed in the substrate 100 and has trenches 106 which are arranged in parallel and extend in the direction of the crucible. The well area 1〇4 is, for example, a 井-type well area. The isolation structure 102 is, for example, disposed in the substrate 1 to isolate the memory cell lines 122. The isolation structure 1〇2 is, for example, a shallow trench isolation structure, and the material is, for example, oxidized oxide. The memory cell row 122 is composed, for example, of a plurality of memory cells 124, each of which includes a word line 114, a composite layer U2, a doped region (source line) 1〇8, and a doped region (bungee region). ) ιι〇, bit line 116 and bit line 17 1285411 umbrella 9twf.d〇c/g 118. The word line 114 is disposed, for example, in the base loo, fills the corresponding trench 106, and extends in the trench 1〇6 to connect the memory cells 124 of the same column. The material of the sub-line Π 4 is, for example, a mixed polycrystalline spine. The composite layer 112 is disposed, for example, between the word line 114 and the substrate 1〇〇. The composite layer 112 is composed of, for example, a dielectric layer 112a, a charge storage layer U2b, and a dielectric layer 112c. The material of the dielectric layer 112a and the dielectric layer n2c is, for example, yttrium oxide, and the material of the charge storage layer 112b is, for example, nitrogen. Pupation or doping of polycrystalline stone. The doped regions (source lines) 1〇8 are, for example, disposed in the substrate 1〇〇 below the corresponding trenches 1〇6, and are shared by the memory cells 124 of the same column. The doped region 108 is, for example, an N-type doped region. The doped regions (drain regions) 11 〇 are, for example, substrates disposed on both sides of the trenches 1〇6, and are numbered in the same-memory cell row 122 along the direction of the ,, and can be divided into the second η·1 ( As shown in FIG. 2, the doping regions 11 (M and 11 〇 _3) and the second n (such as the doping region 11 〇 2 in FIG. 2), n is an integer greater than or equal to i, and adjacent two memories The body phantom 24 shares a doped region UG. The pad region 110 is, for example, an N-type doped region. The bit line 116 and the bit line 118 are, for example, disposed on the substrate 1 and extend in the direction of X. The line 116 is electrically connected to the push of the 2n_i, and the area no is, for example, the doped region 11 (M and 11〇_3). The bit line ι 8 is electrically connected to the doped region (10) of the 2nd n (for example, The doping region ug_2). The material of the bit line 116 and the bit line 118 is, for example, metal tungsten. Further, the non-volatile memory array may further include a conductive plug 2〇. The conductive plug 120 is placed on the substrate. 1〇〇, used to connect the w 1285416 library 9twf.doc / g doped poor region, such as the doping region ii (M and u 〇 _3) and the bit line 2n 唬 doped region 110 (for example, doping Miscellaneous region 1102) and bit line 118. Example of material of conductive plug 12〇 Such as polycrystalline germanium.

In the above non-volatile memory array, each memory cell can be divided into a first _ memory cell located at each word line 114_ = a second memory cell m_2. The first memory cell 124 shares a word line 114, a doped region 1〇8 and a composite layer with the second memory cell M-2: 12' and the adjacent two first memory cells 124 share a μμ No. 1 of the dolo area (for example, doped region 11 (M or 11 〇 _3), and two adjacent second memory cells 124-2 share a second doped region 第 of the 2nd (for example) Is a doped region ιι〇2). That is, the memory cell connecting the doped region 110 to the bit line 116 is defined as a first memory cell 44, and the memory cell connecting the doped region 11A to the bit line 116 is defined as The second memory cell 124-2. The non-volatile memory structure described above has a vertical memory cell structure' as a non-volatile memory structure of a single memory cell. In addition, the same memory of the non-volatile memory structure In the cell row 122, since there are separated bit lines 116 and bit lines 118, two memory cells in the same memory cell can be simultaneously programmed/read/erase. Figure 3 is A circuit diagram of a non-volatile memory according to an embodiment of the present invention. Referring to FIG. 3, the non-volatile memory proposed by the present invention The array includes word lines WL1 to WL4, source lines SL1 to SL4, bit lines BL1 to BL8, and memory cells Mil to M44. The memory cells Mil to M44 are arranged in an array, M1 1 to M14, M21 〜 M24, M31 ~ M34, M31 ~ M34, 12 8 5 41 bees 9twfcloc / g each component one heart): 3⁄4 cell line, Mil~M41, M12~M42, M13~M43, M14~M44 each constitute a memory cell. The structure of each memory cell is as shown in Fig. 2 above, for example, having a gate, a source region, a dipole region, and a charge storage layer. The direction in which the word lines WL1 WL WL4 extend along the direction of γ in a χ γ plane is, for example, the direction of the columns in the memory array, and the direction of X is, for example, the direction of the rows in the memory array, and the word lines WL1 WL WL4 The gates of the memory cells used to connect the same memory cell column. For example, the word line WL1 is used to connect the gates of Mil to M41, and so on, the word lines WL2, WL3, and WL4 are used to connect the gates of M12 to M42, M13 to M43, and M14 to M44, respectively. The source lines SL1 to SL4 extend in the Y direction, and the source lines SL1 to SL4 are respectively connected to the source regions of the memory cells of the same memory cell. For example, the source line SL1 is used to connect the source regions of Mil to M41, and the source lines SL2, SL3, and SL4 are connected to connect the source regions of M12 to M42, M13 to M43, and M14 to M44. The bit lines BL1 to BL8 are grouped by two bit lines, and the bit lines bli and BL2 are a group 'extending in the direction of X. In the same memory cell row, the drain regions are numbered in the direction of the row, and can be divided into 2n-1 and 2n, and η is an integer greater than or equal to 1. In the bit line group formed by the bit lines bli and BL2, the bit line BL1 is connected to the second n-1th bungee region in the memory cell line composed of M1 1 to M14, and the bit line BL2 is connected to the memory cell line. The bungee area of No. 2n. And so on, the bit lines bl3 and BL4 are one bit line group, the bit lines BL5 and BL6 are one bit line group, and the bit line BL7 20 12854 l^^twf.doc/g = medium first = group. These bit line groups are respectively connected to the bungee region of the 2nd·1 #b of the tearing lamp and the non-polar zone of the %th. f down, taking the memory unit Mu and the body in Fig. 3 as an example, = the operation method of the scaly dragon of the present invention. Since the operation method: the definition of the source line and the bit line will be different because the bit to be operated is the upper element: in the following description, the source lines su to SL4 are collectively referred to as the wires SL1 to SL4. Line bli~bl wire BU~BL8 to avoid confusion. FIG. 7 is a schematic view of a stylized operation of the present invention. FIG. 8 to FIG. 11 are diagrams showing a read operation of the present invention. FIG. The non-volatile memory structure of FIG. 4 to FIG. 10 has been reviewed in FIG. 2 and FIG. 3, and the details are not described herein again. ~ First 'Please Mai Zhao Figure 4' When the stylized operation of the upper-A bit of the selected memory cell Mil is performed, the first voltage of the corresponding wire is, for example, 5 volts, in the selected first-memory month. The wire SL1 is applied - the second voltage, for example Q volts, is applied to the selected word wu - the third voltage, for example, the # % voltage is greater than the second voltage, and the selected first =1 ^ ^ ^ ^ The three voltages are greater than the critical value of the first memory cell A = °2 on the same day 1', the base_upper and other green selected memory banks please refer to Figure 5, the second memory cell of the selected memory cell is simple 21 12854 Μ99- When the bit above 8β is programmed, a seventh voltage is applied to the corresponding wire BL2, for example, 5 volts, and an eighth voltage is applied to the wire SL1 of the selected second memory cell b, for example, volts. Applying a ninth voltage to the word line WL1 of the selected second memory cell B, for example, 12 volts, wherein the seventh voltage is greater than the eighth voltage to program the selected second memory cell B above the bit, ninth The voltage is greater than the threshold voltage of the first memory cell a. On the same day, a voltage of 〇V can be applied to the sub-line WL2, the line BL1 and the line SL2 of the other unselected memory cells M12. Referring to FIG. 6, when the first memory cell A and the second memory cell B of the selected memory cell Mil are programmed, a fifteenth voltage is applied to the corresponding wires BL1 and BL2. For example, a 5 volt stomach applies a sixteenth voltage to the wire SL1 of the selected memory cell Mil, for example, 0 volts, and a seventeenth voltage is applied to the word line WL1 of the selected memory cell Mn, for example, 12 Volt, the fifteenth voltage of the towel is greater than the sixteenth voltage, to program the selected first memory cell A and the second e k, cell B. At the same time, a voltage of 〇V can be applied to the substrate (10) and other word lines WL2 and wires su of the uncharged memory cell M12. Please perform a stylized operation on the corresponding memory cells BL1 and BL2 of the selected memory cell MU when programming the @7' J5] The voltage, for example, volts: a fifteenth voltage 'for example, 5 volts' is applied to the wire su of the selected memory cell M11, and the word line 22 12854 WU of the selected memory cell Mn is applied - the seventeenth voltage, For example, 12 volts to programmatically select the selected first-small cell A and the second memory cell B. At the same time, a voltage of - (four) volts can be applied to the memory cell Mi2^WL2 and the wire SL2 on the substrate 1 and other cells. The son of the line, please refer to Figure 8, for the selected #, 阴辨留_

Hfrn~ body 70 first memory cell

When the dead bit is in the Wei operation, a fourth voltage, such as volt, is applied to the selected wire BL1 of the first memory cell A, and the first memory cell A has a different guiding parameter ST 1 such as 馀τ. , 疋之之

Sacrifice, Yu, the five voltages of the brother, for example, 1 volt, the brother of the 圮 圮 圮 圮 的 的 的 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加The threshold voltage before the first memory cell A is not programmed, is less than the threshold voltage after the stylization of the first memory cell A, to read the selected first sympathetic cell body, the early M12 son 70 line hunger 2 The voltage of volts is applied and a voltage of one volt is applied to the wire BL2.

Referring to item 9, when a read operation is performed on the bit cell of the second memory cell B of the selected memory cell Mil, a tenth voltage is applied to the wire BL2 of the selected second memory cell b, for example, 〇 Volt, applying an eleventh voltage to the selected first delta k, cell B wire SL1, for example, i volt stomach 'applies a twelfth voltage to the word line wu of the selected second memory cell B, for example Is 3 volts, wherein the tenth voltage is less than the eleventh voltage, and the eleventh voltage is greater than the threshold voltage before the second memory cell B is unprogrammed, and is smaller than the threshold voltage after the second memory cell B is programmed to read the selected voltage. The second memory cell B is above the bit. At the same time, a voltage of Q volts can be applied to the substrate 1 〇〇 and other word lines WL2 of the memory single S M12 of the unselected 23 12 8 3 4 ΐ umbrella 9 twf.d 〇 c / g, and Wire BL2 applies a voltage of 1 volt. Referring to the figure, when the read operation is performed on the first memory cell A and the second memory cell B of the selected memory cell Mu, the corresponding wires BL1 and BL2 are applied with an eighteenth voltage, for example, 〇 Volt, a tenth voltage 'for example, 1 volt' is applied to the wire su of the selected memory cell M11 to apply a twentieth voltage to the selected word line WL1 of the memory cell, for example, 3 volts, of which tenth The eight voltages are less than the nineteenth to read the selected first memory cell A and the second bit cell B. At the same time, a 〇 特 疋 上 上 上 上 施加 基底 基底 1 1 1 1 1 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定 选定When the bit cell under the memory cell B performs a read operation, the corresponding wires BU and BL2 are applied - the nineteenth f-voltage, for example, j-characterized by applying a voltage to the wire su of the selected memory cell M11, for example, 1 volt. The twentieth voltage, for example, 3 volts, is applied to the character green WL1 of the selected memory cell Mil to read the selected first memory cell A and the second memory cell B lower bit. At the same time, at

A voltage of 0 volts is applied to the upper and other unselected memory cells M12. L 士 凊 Refer to item 12, the above non-volatile memory is erased, and a thirteenth voltage is applied to the substrate 1 ,, for example, a 12 volt memory single AMU and a word line And muscle 2 force 1 - brother fourteen voltage, for example, 〇 volt, where the thirteenth voltage is greater than the twenty-fourth 24,854,541 umbrella 9twf.d〇c / g four voltage to use FN tunneling effect on the memory unit Mil and The younger brother of M12 has recalled cell A and second memory cell B for erasure. At the same time, the wire SL1, the wire BL1, and the wire BL2 can be floated, that is, no voltage is applied.

The above-mentioned operation method for the non-volatile memory proposed by the present invention can operate on one memory cell of a selected memory cell, or can simultaneously operate two memory cells of one memory cell. In addition, the fine-grained method of the non-volatile memory proposed by the present invention can operate on selected memory cells of a plurality of selected memory cells. In this way, it is possible to operate (4) the memory unit according to the operation requirements. In summary, the present invention has at least the following advantages: 1. The non-volatile memory structure of the present invention, because the separated bits can simultaneously align two memory cells with the same memory. / erase operation. Dingbu Wang • Section (4) Non-volatile memory manufacturing method

The word line, source line and secret area can effectively shorten the production cycle. I Private 3. According to the face line of the present invention, it is easier to use the 矣 method to perform the operation. Mi,,, (4) 4' is limited to the memory of a single six in the "such as the scope of the "and within the scope" can be made a little more: Lai not 25 12854 l_99twf d〇c / g range s as defined by the scope of the patent application BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1A to FIG. 1D are schematic perspective views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. FIG. 2 is not a view of an embodiment of the present invention. FIG. 3 is a circuit diagram of a non-volatile memory according to an embodiment of the invention. FIG. 4 to FIG. 7 are schematic diagrams showing a stylized operation according to an embodiment of the present invention. 8 to FIG. 11 are schematic diagrams showing a read operation according to an embodiment of the present invention. FIG. 12 is a schematic diagram showing an erase operation according to an embodiment of the present invention. [Description of Main Components] 100: Substrate 102: Isolation Structure 104: well region 106: trench 108 · doping region (source line) 110, 110-1, 110-2, 110-3: doped region (drain region) 112: composite layer 112a, 112c: dielectric Layer 112b: charge storage layer 114, WL1 WLWL4: word line 26 128541499twfdoc/g 116, 118 , BL1~BL8 ··bit line (wire) 120: conductive plug 122: memory cell line 124 · memory unit 124-1: first memory cell 124-2: second memory cell SL1~SL4: source Line (wire)

Claims (1)

128541499twfdoc/g further includes a second dielectric layer disposed above the charge storage layer. 8. A non-volatile memory sheet as described in claim 7 wherein the material of the dielectric layer comprises oxidized stone. 9. The non-volatile memory sheet of claim 1, wherein the material of the conductive plug comprises a metal. 10. A non-volatile memory device as claimed in claim 1, wherein the material of the first and second wires comprises metal tungsten. 11. A non-volatile memory array comprising: a substrate having a plurality of trenches in the substrate, the trenches being arranged in parallel and extending in a column direction; a plurality of memory cells being memorized by a plurality of memory cells The body unit comprises: hΘ/: a word line disposed in the channel of the face channel and extending in the groove to connect the memory cells of the same column; - a storage layer disposed on the word line and the channel - the first doped region i is shared by the corresponding memory cells of the same column below the trench; * hemiplegia: hetero region and - third doped region, respectively In the substrate on both sides of the trench; the first &quot;1 wire and the second wire are arranged in parallel on the substrate, and are electrically connected to the second doped region and the third one The substrate is provided with a miscellaneous region; and a plurality of isolation structures are connected to the wire from the bottom of the first-doped elementary channel, and the plurality of isolation structures are disposed in the substrate, for isolating the memory cells. The second doping included in the same row of memory cells The regions and the third doped regions are staggered, and two adjacent memory cells share one of the second doped regions or the third doped regions. The non-volatile memory array of claim 11, further comprising a plurality of conductive plugs disposed on the substrate for connecting the second doped regions and the first a wire, the third doped region and the second wires and the first doped regions and the third wires. 13. The non-volatile memory array of claim 11, wherein the isolation structures comprise shallow trench isolation structures. 14. The non-volatile memory array of claim 11, wherein the conductor layers are made of, for example, doped polysilicon. The non-volatile memory array of claim 11, wherein the material of the charge storage layer comprises tantalum nitride. 16. The non-volatile memory array of claim 11, further comprising a plurality of first dielectric layers disposed between the charge storage layers and the trench surface. 17. The non-volatile memory array of claim 16, wherein the material of the first dielectric layer comprises yttrium oxide. 18. The non-volatile memory array of claim 11, further comprising a plurality of second dielectric layers disposed between the charge storage layers and the word lines. 19. The non-volatile memory array 12854 li4^9twfd〇c/g column of claim 18, wherein the second dielectric layer comprises yttrium oxide. 20. The non-volatile memory array of claim 11, wherein the material of the conductive plugs comprises polysilicon. 21. The non-volatile memory array of claim 11, wherein the first wires and the second wires are made of metal tungsten. 22. A method of making a non-volatile memory, comprising: providing a substrate; Forming a plurality of isolation structures in the 6-well substrate, wherein the isolation structures are arranged in parallel and extend in a first direction; a plurality of trenches are formed in the substrate, the trenches are arranged in parallel, and in a second direction Extending, and the second direction intersects the first direction; forming a plurality of first doped regions in the substrate under the trenches; forming a plurality of second doped regions in the substrate on both sides of the trenches a plurality of third doped regions, wherein the third doped regions are staggered in the second direction; the plurality of charge storage brows are formed on the surface of the substrate in the trenches a plurality of word lines filling the trenches are formed on the substrate; second, a plurality of first wires are formed on the substrate, and a plurality of second wires are electrically connected to the second doped regions and the The three doped regions ', and the first wires and the second wires are arranged in parallel and extend toward the four. The non-volatile manufacturing method of claim 22, further comprising forming a plurality of scale plugs 1 on the substrate for connecting the second doped regions and the first wires And the first == 31 128541^9twf.d〇c/g miscellaneous area and the second wires. [24] The method of claim 22, wherein the method of forming the third doped regions of the H-th body comprises an ion implantation method, a doping region, and a two-party m The material of the charge storage layer includes the nitrite. Manufactured by the 22nd __ memory of the dynasty-first dielectric i under the charge storage layer and the substrate between the base of the non-volatile memory of the 26th paragraph The material of the first dielectric layer includes yttrium oxide. The / / 8b towel of the non-volatile memory of the 22nd item of the patent scope is further included to form a second dielectric layer between the charge storage layer and the word line. The method of the non-volatile memory of the patent application, wherein the second dielectric layer comprises yttrium oxide. The method of claim 22, wherein the method of forming the word lines comprises: forming a layer of conductive material on the substrate and filling the trenches And removing the layer of the conductor material formed outside the trenches. The method of non-volatile memory according to claim 22, wherein the layer of the conductor material formed outside the trenches is removed to include a chemical mechanical polishing method. 32 128541 Umbrella twfdoc / g 32 - a non-volatile memory operation method, suitable for a memory cell array arranged in rows / columns, the memory cell array is composed of a plurality of memory cells, each of the memory cells including a word line disposed in one of the bases, in the channel, and extending in the trench, and connecting the memory cells of the same column to a single charge and a charge storage layer disposed on the word line and the substrate And a first doped region disposed in the corresponding underlying trench, and shared by the same 5 丨 丨 单元 unit, a second doped region, and a third doped region And a first wire and a second wire respectively disposed on the two sides of the trench, disposed on the substrate, extending in a row direction, and the gas is connected to the gas-doped doping And the third doped region, and the adjacent two memory cells share a second doped region or the third doped region, and each memory cell includes a first pixel on each side of the word line a memory cell and a second memory cell, the method of operating the non-volatile memory </ RTI> &gt;# performs a stylization operation, a first voltage is applied to the first wire corresponding to the selected first memory cell, and a first voltage is applied to the == doped region of the selected first memory cell a second voltage is applied to the = element line of the selected first memory cell, wherein the first voltage is greater than the second voltage and the upper memory of the first memory cell is The third voltage is greater than a threshold voltage of the memory cell; and the first wire corresponding to the first memory cell selected by the first memory cell applies the third voltage to the first doped region of the selected first memory cell Applying the first private voltage to the word line of the memory cell to apply the third circuit to embellish one of the first memory cells. 33. Non-volatile memory as described in claim 32 of the patent scope 33 I2854t Umbrella twfd〇c/g operation method, comprising: ▲ during the stylization operation, applying a seventh voltage to the second wire corresponding to the selected second memory cell, and selecting the second memory cell Applying a voltage to the first doped region, applying a voltage to the ninth voltage of the selected second memory cell, wherein the seventh voltage is greater than the eighth electrical f. The second memory cell, the upper voltage, the ninth voltage is greater than the threshold voltage of 7 σ 丨 丨 早 早 ; 7 ; = the second wire corresponding to the selected second memory cell applies the eighth voltage 'the selected first voltage in the first doped region of the selected second memory cell' to the selected second memory cell The word line applies the ninth electric S' to program a lower bit of the second memory cell. 34. The method for operating a non-volatile memory according to the invention of claim 1, wherein: when reading the upper bit of the second memory cell, selecting the second ^1* Corresponding to the second wire, a tenth voltage is applied, and a tenth voltage is applied to the first-# miscellaneous region of the selected memory cell, and the word line of the selected first phase of the memory cell Applying a twelfth voltage, wherein the tenth electric charge is less than the third tenth voltage, the twelfth voltage is greater than a threshold voltage before the second memory cell is unprogrammed, and sweeping the threshold after the second memory ageing a voltage; and when reading the lower bit of the second memory cell, applying the tenth voltage to the second wire corresponding to the selected second memory cell, and selecting the second memory cell The doped region applies the tenth voltage, and the twelfth voltage is applied to the word line of the selected second memory cell. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The first wire corresponding to the cell is applied with a fourth voltage, and a fifth voltage is applied to the first doped region of the selected first memory cell, and the word line of the first cell is selected Applying a sixth voltage, wherein the fourth voltage = at the fifth voltage 'the sixth is greater than the first memory cell is not programmed to be a secret, less than the threshold voltage after the first memory cell is programmed; When the lower cell of the first memory cell is purchased, the fifth voltage is applied to the first wire corresponding to the selected first memory cell, and is applied to the first change region of the selected first memory cell. The fourth voltage applies the sixth voltage to the word line of the selected first memory. β 36 · The method for inserting non-volatile memory as described in claim 4 (4) 包括 32 includes applying a thirteenth voltage to the substrate during the erasing operation, and selecting the memory unit The word line is applied with a fourteenth ❿ I voltage, wherein the twelfth voltage is greater than the fourteenth voltage to be erased by the FN tunneling effect. 35