CN103545261B

CN103545261B - There is three-dimensional nonvolatile storage cell array of inlaying wordline and forming method thereof

Info

Publication number: CN103545261B
Application number: CN201210242993.4A
Authority: CN
Inventors: 陈士弘; 施彦豪; 吕函庭
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2012-07-13
Filing date: 2012-07-13
Publication date: 2016-03-16
Anticipated expiration: 2032-07-13
Also published as: CN103545261A

Abstract

The invention discloses and a kind of there is three-dimensional nonvolatile storage cell array of inlaying wordline and forming method thereof, this memory cell array is such as that the line of material partial oxidation of silicon is formed on non-volatile memory structural laminate, by the plurality of unoxidized silicon line of mid portion removing of the silicon line from multiple partial oxidation, and retain the line of the plurality of oxidation of Outboard Sections of silicon line of the plurality of partial oxidation, and forming wordline raceway groove among the line of material of this partial oxidation, then wordline is formed on the non-volatile memory structural laminate in wordline raceway groove.

Description

There is three-dimensional nonvolatile storage cell array of inlaying wordline and forming method thereof

Technical field

The invention relates to high density memory Set, particularly about there is multi-level memory cell to provide the arrangement of 3 D memory array in storage device.

Background technology

In the example of a 3 D memory array, each comprises the staggered multiple ridge shape of rectangular semiconductor laminated and rectangular oxide, and these ridges are by being such as the electric charge storage layer of polysilicon or the charge trapping material covering of similar silica silicon nitride silica.Wordline orthogonal with ridge and along shape ground, to access the memory cell of this three-dimensional memory cell array.Such as that the insulated wire of silica is orthogonal with ridge and along shape ground, by adjacent wordline electrical isolation each other.

But, formed silicon oxide line by adjacent wordline each other electrical isolation be not one and very simply work.Fig. 1 and Fig. 2 shows in different process the problem that the wordline that manufactures cubical array and silicon oxide line meet with.

Fig. 1 shows the schematic diagram of a three-dimensional memory array device, and wherein polysilicon word line is formed before the silica separating wordline, and residual polycrystalline silicon thing can form the bridge of leading do not predicted causes electric connection between adjacent word line.

Semiconductor strips lamination 11,13,15 is separated by insulating material rectangular 10,12,14,16.The rectangular lamination of staggered semiconductor/silica is covered by the electric charge storage layer 26 being such as ONO or ONONO.Polysilicon etch unnecessary between adjacent polysilicon wordline by covering the lamination of the rectangular and electric charge storage layer of staggered semiconductor/silica with polysilicon, and is removed to form raceway groove between adjacent polysilicon wordline by polysilicon word line 55.After unnecessary polysilicon is removed in etching, silicon oxide line is formed to isolate adjacent polysilicon wordline.

Because the height of the rectangular lamination of staggered semiconductor/silica of electric charge storage layer covering is relative to the high-aspect-ratio representated by the ideal distance between adjacent word line.Consequently, residual polycrystalline silicon thing 56 cannot be etched removal.Although have silica-filled in raceway groove after the polysilicon etch, residual polycrystalline silicon thing 56 causes the electric connection between adjacent word line (only show wordline in figure, do not show adjacent word line).

This electric charge storage layer is filled with a part for the rectangular lamination of this staggered semiconductor/silica, causes the silica defect in region 27.Silica defect in region 27 is because the rectangular lamination of clean staggered semiconductor/silica when preparing formation electric charge storage layer caused.This hole is filled by residual polycrystalline silicon thing 56, and it can cause the electric connection between adjacent word line (only show wordline in figure, do not show adjacent word line).

Fig. 2 shows the schematic diagram of a three-dimensional memory array device, and wherein silicon oxide line is formed before polysilicon word line, and the bridge of leading that silicon monoxide hole allows residual polycrystalline silicon thing to be formed not to be predicted causes electric connection between adjacent word line.

Semiconductor strips lamination 11,13,15 is separated by silica rectangular 10,12,14,16.The rectangular lamination of staggered semiconductor/silica is covered by the electric charge storage layer being such as silica 20-silicon nitride 21-silica 22.Silica unnecessary between adiacent silica line etching by covering the lamination of the rectangular and electric charge storage layer of staggered semiconductor/silica with silica, and is removed to form raceway groove between adiacent silica line by silicon oxide line 45.After unnecessary silica is removed in etching, inlay in the raceway groove that polysilicon word line is formed between adiacent silica line.

Silicon oxide line 45 has a hole 46.Inlaying the step in the raceway groove that polysilicon word line is formed between adiacent silica line, silica hole 46 can insert polysilicon, causes to produce between the adjacent polysilicon line of silicon oxide line 45 both sides to be electrically connected.

An extra problem is the electric charge storage layer quality covering the rectangular lamination of staggered semiconductor/silica.But after the silica that etching is unnecessary, silica etch process can injure the electric charge storage layer below unnecessary silica.The performance of storage device so can be affected for electric charge storage layer injury.Be such as ONO to the electric charge storage layer with outside silica, be very difficult to only remove unnecessary silica and selective etch that silica outside electric charge storage layer can not be removed.

Fig. 3 shows the top view of a three-dimensional memory array device, and wherein ONO electric charge storage layer was still formed after silicon oxide line before polysilicon word line, caused a large-size of this array.This technological process display (i) forms staggered silica/semiconductor strips lamination 18, (ii) form that silicon oxide line 42 is orthogonal with silica/semiconductor strips lamination and along shape, (iii) formation is such as the electric charge storage layer 28 of ONO or polysilicon.This electric charge storage layer can cover staggered silica/semiconductor strips lamination 18.This graphic electric charge storage layer that do not show can cover staggered silica/semiconductor strips lamination 18, so can see the lateral dimensions of electric charge storage layer.This technological process is bad, because unit storage unit size is enlarged into the twice of charge storage layer thickness in side direction.

Describe one in the U.S. Patent Application No. 12/347331 of applying on January 10th, 2012 and inlay wordline.The present invention then depicts extra inlays wordline technology.In many embodiments of U.S. Patent Application No. 12/347331, there is shorter technological process, and by further for word line pitch micro, or less distance can be had in adjacent word line spacing in many embodiments of the present invention.

Therefore need the three dimensional integrated circuits memory construction that a kind of low manufacturing cost is provided, it comprise reliably, very little memory element, and improvement has between the relevant process island of the consecutive storage unit serial lamination of grid structure.

Summary of the invention

Technology described herein comprises the method for a kind of formation one three-dimensional nonvolatile storage cell array, and the method comprises:

Form more than first line of material on multiple non-volatile memory structural laminate, this more than first line of material is by separate for this more than first line of material by more than first wordline raceway groove.In some described herein embodiment, in order to form many webs stockline, the material layer being such as silicon is formed on multiple non-volatile memory structural laminate, and the excess stock layer being such as silicon is removed to retain more than first line of material since then in layer and forms more than first wordline raceway groove between more than first adjacent line of material.

The structure of multiple partial oxidation is that the line of material by being oxidized these more than first line of material both sides produces in this more than first line of material.The structure of the plurality of partial oxidation comprises many oxide lines and more than first line of material narrowed are bordered on, and the line of material narrowed wherein in these more than first line of material narrowed has the narrower width of line of material in comparatively this more than first line of material.

These more than first line of material narrowed that removing and these many oxide lines are bordered on, to form more than second wordline raceway groove.

Formed on the plurality of non-volatile memory structural laminate of many wordline in this more than first wordline raceway groove and this more than second wordline raceway groove.

In some described herein embodiment, the plurality of line of material comprises silicon line.In certain embodiments, the plurality of silicon line comprises amorphous silicon, polysilicon and monocrystalline silicon at least one.Polysilicon as used herein can by be such as amorphous silicon or monocrystalline silicon etc. other silicon materials replace.

In other described herein embodiments, it is such as the metal wire of tungsten that the example of line of material can be, and its oxidation becomes tungsten oxide (WO _x).It is relevant to technique for successfully metal wire being oxidized to insulation oxide, and can along with the concentration change of oxygen.

In other described herein embodiments, line of material comprises semiconductor line.

In many embodiments described herein, the electric charge storage layer come to harm in etching process can be repaired.After removing covers these more than first line of material narrowed of the plurality of non-volatile memory structural laminate, etching covers oxide exposed in this more than second wordline raceway groove of the plurality of non-volatile memory structural laminate.In certain embodiments, exposed oxide is that etching is until by out exposed for the silicon nitride of the plurality of non-volatile memory structural laminate covered in this more than second wordline raceway groove.Exposed oxide etching so can remove the oxide that is hurt that originally can affect storage device performance.This etched oxide is replaced by new oxide.Oxide is formed in this more than second wordline raceway groove of the plurality of non-volatile memory structural laminate of covering.The new oxide of the etched exposed oxide of replacement like this can produce preferably storage device performance.In various embodiments, oxide can be deposition, and/or is oxidized generation by the silicon nitride that will cover in this more than second wordline raceway groove of the plurality of non-volatile memory structural laminate.

In some described herein embodiment, cover these more than first line of material narrowed of the plurality of non-volatile memory structural laminate in removing before, in this more than first wordline raceway groove, form more than second line of material.Form wordline in this more than first wordline raceway groove before, remove this more than second line of material in this more than first wordline raceway groove at least partly when the line of material that removing these more than first narrows.After remove this line of material in wordline raceway groove, wordline can be formed in wordline raceway groove.

In some described herein embodiment, removing these more than first line of material narrowed and retaining at least one wordline raceway groove of this more than second wordline raceway groove is such as the retained material of silicon.After these more than first line of material narrowed of removing, the retained material at least one wordline raceway groove of this more than second wordline raceway groove being such as silicon is oxidized.

In some described herein embodiment, an oxidation line of these many oxidation line has hole.After these more than first line of material narrowed of removing, the retained material being such as silicon is carried out being oxidized to put small part fill this hole at least one wordline raceway groove of this more than second wordline raceway groove.

In some described herein embodiment, forming these many wordline is mosaic crafts.

In some described herein embodiment, contain the line of material of these more than first line of material both sides on first and second line of material surface in oxidation package before, form the oxidation mask on the 3rd line of material surface covering this more than first line of material, the 3rd line of material surface is by this first and second line of material surface conjunction.This oxidation mask slows down the oxidation on the 3rd line of material surface when carrying out this first and second line of material surface oxidation.In certain embodiments, when fill be such as the material of silicon within this more than first wordline raceway groove time, deposition is such as that the material of silicon is at least in part on this oxidation mask.This oxidation mask is removed after this first and second line of material surface oxidation of oxidation.3rd line of material surface is because it can be have the upper surface slowing down oxidation rate that oxidized mask covers.After removing this oxidation mask, when remove these more than first narrow line of material time, to remove in this more than first wordline raceway groove at least in part this be such as the material of silicon.

In some described herein embodiment, before this more than first wordline raceway groove of formation, formed and comprise the multiple rectangular semiconductor separated by insulating material and charge storing structure and be covered in the plurality of non-volatile memory structural laminate on multiple rectangular semiconductor.In addition, this charge storing structure comprises silicon monoxide-silicon-nitride and silicon oxide-silicon nitride-silicon oxide silicon structure (such as energy gap engineering silicon-oxide-nitride-oxide-silicon structure BE-SONOS).In an example, this charge storing structure comprises a hafnium oxide layer.In another example, charge storing structure covers the plurality of semiconductor strips, and this charge storing structure comprises dielectric layer and has the dielectric constant that a dielectric constant is greater than silica.

The present invention also discloses the another kind of method forming a three-dimensional nonvolatile storage cell array.The method comprises:

Form the silicon line of multiple partial oxidation on multiple non-volatile memory structural laminate, the silicon line of the plurality of partial oxidation has multiple unoxidized silicon line in the mid portion of the silicon line of the plurality of partial oxidation and the line of multiple oxidation in the Outboard Sections of the silicon line of the plurality of partial oxidation.

By the plurality of unoxidized silicon line of the mid portion of the silicon line from multiple partial oxidation removing, and retain the line of the plurality of oxidation of Outboard Sections of silicon line of the plurality of partial oxidation, and form multiple wordline raceway groove among the silicon line of the plurality of partial oxidation.

Formed on the plurality of non-volatile memory structural laminate of many wordline in the plurality of wordline raceway groove.

In some described herein embodiment, after removing covers the plurality of unoxidized silicon line of the plurality of non-volatile memory structural laminate, etching covers oxide exposed in this more than second wordline raceway groove of the plurality of non-volatile memory structural laminate.Formation oxide covers the plurality of non-volatile memory structural laminate in the plurality of wordline raceway groove.

In some described herein embodiment, the step of silicon line on multiple non-volatile memory structural laminate forming multiple partial oxidation comprises:

Form the oxidation mask of the silicon line upper surface of these the many silicon lines covering the plurality of non-volatile memory structural laminate; And

By two exposed surface oxidations of silicon line in these many silicon lines.

The present invention also discloses a kind of integrated circuit with three-dimensional nonvolatile storage cell array.This integrated circuit comprises the wordline of many double patternings; These many wordline of many silicon oxide line separating adjacents; And multiple non-volatile memory structural laminate is in this cubical array.The wordline of this double patterning is produced by multiple patterning step or multiple-exposure and multiple etching step.

The plurality of non-volatile memory structural laminate is covered by these many wordline and this many silicon oxide lines, the plurality of non-volatile memory structural laminate comprises a silicon nitride layer, the plurality of non-volatile memory structural laminate comprises a Part I and to be covered by these many wordline and a Part II is covered by these many silicon oxide lines, and this silicon nitride layer in this Part I has the less thickness of this silicon nitride layer in comparatively this Part I.

The many different embodiment of many different technologies schemes is described herein.

Object of the present invention, feature, and embodiment, graphic being described of arranging in pairs or groups in the chapters and sections of following embodiments.

Accompanying drawing explanation

Fig. 3 shows the top view of a three-dimensional memory array device, and wherein ONO electric charge storage layer was still formed after silicon oxide line before polysilicon word line, caused a large-size of this array.

Fig. 4 shows the some processes generalized section of manufacture one storage device, and shows respective formed multiple parallel semiconductor strips and separated by oxide stripes and be arranged to multiple ridge shape lamination.

Fig. 5 shows the some processes generalized section of manufacture one storage device, and shows respective formed oxide-nitride-oxide data storage layer on the multiple ridge shape laminations shown in Fig. 4.

Fig. 6 shows the some processes generalized section of manufacture one storage device, and shows respective the formed polysilicon lines with suitable shape lower surface on ridge shape lamination multiple shown in Fig. 5.

Fig. 7 shows the some processes generalized section of manufacture one storage device, and display is formed on the polysilicon lines of oxidation mask in Fig. 6.

Fig. 8 shows the some processes generalized section of manufacture one storage device, and the polysilicon lines of display in Fig. 7 separately formed silicon oxide line in having on suitable shape lower surface multiple ridge shape lamination.

Fig. 9 shows the some processes generalized section of manufacture one storage device, and display formation polysilicon is filled in the raceway groove in exposed surface and Fig. 8.

Figure 10 shows the some processes generalized section of manufacture one storage device, and display carries out polysilicon etch with by out exposed for the oxide mask in Fig. 9.

Figure 11 shows the some processes generalized section of manufacture one storage device, and the oxide mask in Figure 10 removes by display.

Figure 12 shows the some processes generalized section of manufacture one storage device, and the polysilicon lines in Figure 11 removes by display.

Figure 13 shows the some processes generalized section of manufacture one storage device, and the remaining polycrystalline silicon in Figure 12 is oxidized by display.

Figure 14 shows the some processes generalized section of manufacture one storage device, and the data storage layer of the oxide-nitride-oxide in Figure 13 is removed outer oxide by display.

Figure 15 shows the some processes generalized section of manufacture one storage device, and display forms outside silica separately again in the outside of the data storage layer of silicon-nitride and silicon oxide shown in Figure 14.

Figure 16 shows the some processes generalized section of manufacture one storage device, and display is carried out polysilicon and is filled in exposed surface, and is filled in separately and separates shown in Figure 15 in the wordline raceway groove of silicon oxide line.

Figure 17 shows the some processes generalized section of manufacture one storage device, and the excess polysilicon shown in Figure 16 removes by display separately.

Figure 18 shows the some processes generalized section of manufacture one storage device, and the polysilicon word line formation silicided polysilicon wordline that display is respective in Figure 17.

Figure 19 is the alternate embodiment of Figure 18, the some processes generalized section of display manufacture one storage device, and shows the polysilicon removal above the oxide-nitride-oxide data storage layer on multiple ridge shape laminations respective in Figure 17.

Figure 20 is another alternate embodiment of Figure 18, the some processes generalized section of display manufacture one storage device, and the wordline showing that polysilicon formation outside oxide-nitride-oxide data storage layer exposed on multiple ridge shape laminations respective in Figure 17 and exposed in Figure 19 has metal surface.

Figure 21 is the alternate embodiment of Figure 18, the some processes generalized section of display manufacture one storage device, and is presented at the wordline exposed polysilicon being formed and has metal surface.

Figure 22 shows the comparison diagram of the silicon nitride layer of respective oxide-nitride-oxide data storage layer below wordline lower zone and silicon oxide line.

Figure 23 ~ Figure 25 shows the schematic diagram of different M shape grid.

Figure 26 is a generalized section with a three-dimensional storage part for staggered passage and silicon oxide stack, shows the potential region having " shadow effect ".

Figure 27 is an example with the three-dimensional storage structure of inlaying grid.

Figure 28 shows in Figure 23 the circuit diagram of the example with the three-dimensional storage structure of inlaying grid.

Figure 29 shows the rough schematic view of integrated circuit according to an embodiment of the invention, wherein integrated circuit comprise use there is the three-dimensional NAND gate flash array inlaying grid and column and row and plane decoding circuit described herein.

Figure 30 ~ Figure 37 shows the technique upper schematic diagram of manufacture one storage device.

[main element symbol description]

11,13,15: semiconductor strips lamination

10,12,14,16: insulating material is rectangular

18: staggered silica/semiconductor strips lamination

20,22,24,49: silica

21,23: silicon nitride

25,29: oxide mask

26,28: electric charge storage layer

30,31,41: polysilicon lines

34,35,37,38,151: silicon oxide line

36,39: narrow polysilicon lines

32,43,56,57: remaining polycrystalline silicon

42: silicon oxide line

47: hole

48: dielectric layer

55: polysilicon word line

58,59,61 and 63: polysilicon lines

62,64: metal wire

51: metal silicide

52: vertical polysilicon member

70,71,72,73,74,75,76,77,78,80,82,84: memory cell

96: bit line

106,108: serial selection line

159,162: ground connection selects line

160,161: wordline

112,402,403,404,405,412,413,414,415: rectangular semi-conducting material

402B, 403B, 404B, 405B, 412A, 413A, 414A, 415A: step structure

109,409,419:SSL grid structure

125-1 ~ 125-4,425-1 ~ 425-n: wordline

127,426,427: ground connection selects line GSL

107,128,428: source electrode line

975: integrated circuit

960: there is the three-dimensional NAND gate memory array of inlaying grid

958: plane decoder

959: bit line

961: column decoder

962: wordline

963: row decoder

964: serial selection line

965: bus

967: data/address bus

966: sensing amplifier/data input structure

974: other circuit

969: state machine

968: bias voltage adjustment supply voltage

971: Data In-Line

972: DOL Data Output Line

Embodiment

In the diagram, the semiconductor strips of 3 layers is only shown for simplicity.But, the number of these levels also can be other number be such as 2 layers, 4 layers, 8 layers, 16 layers etc.This storage array is formed on an ic substrate, and it has insulating barrier and is formed at (not shown) on the semiconductor of bottom or other structure.This storage array comprises multiple semiconductor strips lamination (showing 2 laminations in figure) 11,13,15 and insulating material rectangular 10,12,14,16 is staggered.These laminations are ridge shape and extend Y-axis as shown in FIG., make these semiconductor strips 11,13,15 configurations be memory cell serial.In the memory cell serial of mutually level semiconductor strips as the same memory plane.

In order to form rectangular lamination, in an example, semiconductor level and insulating material level utilize is such as the array region that deposited overall is staggered to form in this chip.These semiconductor strips use the semiconductor layer separated by insulating barrier and are formed.Fig. 4 shows lithographic patterning step, and it is used to the ridge shape lamination defining semiconductor strips.The technique being lithographically base can be used to apply carbon containing hard mask for the gap of high-aspect-ratio and reactive ion etch is formed between lamination, and supports many levels.

These semiconductor strips 11,13,15 can be p-type semiconductor material.For example, these semiconductor strips 11,13,15 can be p-type polysilicon or p-type epitaxial monocrystalline silicon.

Alternatively, rectangular semi-conducting material 11,13,15 can be n-type semiconductor.This n-type semiconductor arrangement causes burying-charge capturing storage unit of the vague and general kenel of passage.For example, rectangular semi-conducting material 11,13,15 can be N-shaped polysilicon, or N-shaped epitaxial monocrystalline silicon.The doping content of the rectangular semi-conducting material of typical case's N-shaped is about 10 ¹⁸/ cm ³, the scope of embodiment can be used greatly about 10 ¹⁷/ cm ³to 10 ¹⁹/ cm ³between.Use N-shaped rectangular semi-conducting material to be preferably select for the embodiment without knot because can improve along NAND gate serial conductance and therefore allow higher reading electric current.

Interlayer dielectic rectangular 10,12,14,16 for example can use silicon dioxide, other silica or silicon nitride.These layers can use many different modes to be formed, and comprise the technology such as the low-pressure chemical vapor deposition (LPCVD) that industry knows.

These insulating material being formed at the insulating material 12 between rectangular semi-conducting material 11,13 and the insulating material 14 be formed between rectangular semi-conducting material 13,15 and the corresponding insulating material in other laminations rectangular have approximating or are greater than the equivalent oxide thickness of 40 nanometers, wherein equivalent oxide thickness EOT be the thickness of insulating material orthogonal with the ratio of insulating material dielectric constant according to oxide after thickness.Noun as used herein " about 40 nanometer " be consider about 10% variation, it is the fabrication error of this kind of kenel one exemplary.The thickness of this insulating material can interfere with each other and plays the part of an important role reducing in this structure adjacent level between memory cell.In certain embodiments, the equivalent oxide thickness of this insulating material can be as small as about 30 nanometers and just can reach isolation in semiconductor strips between adjacent level.

This data storage layer can comprise a dielectric charge catch structure.Be silica 22 (separator)-silicon nitride 21 (can be with the layer of compensation)-silica 20 (tunneled holes layer) that a deposited overall result comprises data storage layer shown in figure, in this example, it is covered on multiple semiconductor strips lamination along shape.

This storage material layer can comprise other charge storing structure.For example, the SONOS charge storing structure of energy gap engineering (BE) can be used to replace, and it comprises dielectric tunnel layer, and has inverted U valence band in fact at 0V bias voltage between level.In one embodiment, this multilayer tunnel layer comprises ground floor and is called tunneled holes layer, and the second layer is called can be with layer of compensation and third layer to be called separator.In this embodiment, tunneled holes layer comprises the side surface that silicon dioxide layer is formed at rectangular semi-conducting material, it can utilize as on-site steam produces (in-situsteamgeneration, ISSG) method is formed, and after optionally utilizing deposition, nitric oxide is annealed or in deposition process, adds nitric oxide production mode to carry out nitrogenize.The thickness of the silicon dioxide in ground floor is less than 20 dusts, and be preferably less than 15 dusts, is 10 ~ 12 dusts in a representative embodiment.

In this embodiment, it is be positioned on tunneled holes layer that layer of compensation can be with to comprise silicon nitride layer, and it is that to utilize similarly be the technology of low-pressure chemical vapor deposition LPCVD, uses dichlorosilane (dichlorosilane, DCS) to be formed with the predecessor of ammonia at 680 DEG C.In other techniques, layer of compensation can be with to comprise silicon oxynitride, it utilizes similar technique and nitrous oxide predecessor to be formed.Can be less than 30 dusts with the thickness of the silicon nitride layer in layer of compensation, and be preferably 25 dusts or less.

In this embodiment, it is be positioned to be with on layer of compensation that separator comprises silicon dioxide layer, and its be utilize similarly be LPCVD high-temperature oxide HTO deposit mode formed.Silicon dioxide layer thickness in separator is less than 35 dusts, and be preferably 25 dusts or less.Three layers of tunnel dielectric layer so create " fall U " the valence band energy rank of shape.

The valence band energy rank at the first place to make electric field be enough to bring out tunneled holes by the thin region between this first place and semiconductor body (or rectangular semi-conducting material) interface, and it is also enough to the valence band energy rank behind lifting first place, effectively to eliminate the tunneled holes phenomenon in the composite tunnel dielectric layer behind the first place.This kind of structure, except setting up this three layers of tunnel dielectric layer " fall U " valence band of shape, also the high speed tunneled holes of electric field-assisted can be reached, it also can when electric field exist or only bring out little electric field in order to other operation objects (similarly being the memory cell from memory cell reading data or programming vicinity), and effective prevention charge loss passes through through composite tunnel dielectric layer structure.

In a representational device, storage material layer comprises energy gap engineering (BE) composite tunnel dielectric layer, its thickness comprising the silicon dioxide of ground floor is less than 2 nanometers, and the thickness of one deck silicon nitride layer is the silicon dioxide layer thickness being less than 3 nanometers and a second layer is be less than 4 nanometers.In one embodiment; this composite tunnel dielectric layer comprises ultra-thin silicon oxide layer O1 (being such as less than or equal to 15 dusts), ultra-thin silicon nitride layer N1 (being such as less than or equal to 30 dusts) and ultra-thin silicon oxide layer O2 (being such as less than or equal to 35 dusts) and formed; and under its 15 dusts can started at the interface with semiconductor body or rectangular semi-conducting material or less compensation, increase the valence band energy rank of about 2.6 electron-volts.By a region, low valence band energy rank (high hole tunneling barrier) and high conduction band energy rank, N1 layer and electric charge capture layer can be separated one second and compensate (such as starting at about 30 dust to 45 dusts from interface) by O2 layer.Because second place's distance interface is comparatively far away, the electric field being enough to bring out tunneled holes can improve the valence band energy rank behind the second place, effectively eliminates tunneled holes potential barrier to make it.Therefore, O2 layer can't the tunneled holes of severe jamming electric field-assisted, can promote again simultaneously through engineering tunneling dielectric structure at low electric field time block the ability of charge loss.

The thickness that electric charge capture layer in storage material layer comprises silicon nitride layer is in this embodiment greater than 50 dusts, comprises for example, the silicon nitride of thickness about 70 dust, and it utilizes as LPCVD mode is formed.The present invention also can use other charge trapping material and structure, and comprising similarly is silicon oxynitride (Si _xo _yn _z), the nitride of high silicon content, the oxide of high silicon content, comprise trapping layer of embedded nano particle etc.

Stop dielectric layer in this embodiment in storage material layer is silica, and its thickness is greater than 50 dusts, and is included in this embodiment Chinese style 90 dust, and can use the wet furnace oxidation technique of silicon nitride being carried out wet method conversion.Then can use the silica that high-temperature oxide (HTO) or LPCVD depositional mode are formed in other embodiments.Also other stop dielectric layer material can be used to be such as the high-k material of aluminium oxide.

In a representative embodiment, the thickness of the silicon dioxide in tunneled holes layer is 13 dusts; Can be 20 dusts with the silicon nitride layer thickness of layer of compensation; The silicon dioxide layer thickness of separator is 25 dusts; The silicon nitride layer thickness of electric charge capture layer is 70 dusts; And stop that dielectric layer can be the silica of thickness 90 dust.This grid material can be p+ polysilicon (its work function is 5.1 electron-volts).

Outer oxide 22 in Fig. 5 is sacrifical oxides, again grows up after will being removed again.

Polysilicon lines 30 and 31 along shape is formed on the data storage layer of coated multiple semiconductor strips lamination.These polysilicon lines 30 and 31 are filled in the gap between multiple semiconductor strips lamination.Show two polysilicon lines 30 and 31 in figure, but the polysilicon lines of different number in other embodiment, can be had.Extra polysilicon lines can be formed at along in the Y direction of the turnover page.Adjacent polysilicon lines is separated by the wordline raceway groove being such as raceway groove 33, and it can narrow in subsequent steps.

In the filling step of a high-aspect-ratio, such as, be the electric conducting material of polysilicon with N-shaped or p-type doping, be deposited and be covered on the rectangular lamination of semi-conducting material and insert in the gap between multiple semiconductor strips lamination.Such as that the high-aspect-ratio deposition technique of low-pressure chemical vapor deposition polysilicon can be used for filling the gap 220 between ridge shape lamination completely, even have the very narrow raceway groove being about 10 nanometer scale width of high-aspect-ratio.

One dielectric layer 48 can be silicon nitride as illustrated in the drawing, or silicon dioxide and other silica.This dielectric layer can use many different modes to be formed, and comprises the technology such as the low-pressure chemical vapor deposition (LPCVD) that industry knows.It is such as that the oxide species such as oxygen and water diffuses in this polysilicon layer 44 that this dielectric layer 48 can slow down.

Fig. 7 shows the some processes generalized section of manufacture one storage device, and on the polysilicon lines of display in Fig. 6 and dielectric layer separately form oxide mask.

In a lithographic patterning step, define polysilicon lines 30 and 31 from polysilicon layer 44.In a representative embodiment, the width of polysilicon lines can be between the scope of 500 ~ 1500 dusts.Actual width is must be relevant to the distance between specific subsequent process steps and required wordline width and wordline.This lithographic patterning step defines the critical dimension of this array when using a mask to be such as the high-aspect-ratio raceway groove of raceway groove 33 between etching polysilicon lines, and can not be etched through ridge shape lamination.This high-aspect-ratio wordline raceway groove is separated in the polysilicon lines formed in this step, and is defined in the wordline that subsequent step formed at last, although it can narrow in subsequent steps.Polysilicon can use one to etch the etch process that polysilicon has high selectivity than silica or silicon nitride.Therefore, rely on identical mask and use mutual etch process to be etched through conductor and insulating barrier, it has the technique stopping at bottom insulating barrier.Although be use the etch process with high selectivity to etch, be such as that the exposed oxide layer of outer oxide 22 still can be lost in this etch process.Oxide 22 is that then a sacrifice layer and being etched afterwards grows again in follow-up the technique discussed.Oxide 22 protects silicon nitride and stores core 21.

Polysilicon lines 30 and 31 is formed on the multiple rectangular semiconductor laminated data storage layer of covering along shape.Polysilicon lines 30 and 31 fill between rectangular semiconductor laminated between gap in.Show two polysilicon lines 30 and 31 in figure, but the polysilicon lines of different number in other embodiment, can be had.Extra polysilicon lines can be formed at along in the Y direction of the turnover page.Adjacent polysilicon lines is such as the wordline raceway groove separation of raceway groove 33 by one, and it can narrow in follow-up technique.

At definition polysilicon lines 30 with in the identical lithographic patterning step of 31, oxide mask 25 and 29 defines in dielectric layer 48.It is such as that the oxide species such as oxygen and water diffuses into polysilicon 44 that this oxide mask 25 and 29 can slow down.Therefore, this oxide mask 25 and 29 can slow down the oxidation of the top surface of underlying polysilicon line 30 and 31.

Residual polycrystalline silicon thing 32 in Fig. 7 creates the risk electrically leading bridge being formed and be electrically connected adjacent word line.This residual polycrystalline silicon thing 32 can be oxidized in fig. 8, and eliminate the short-circuit risks that residual polycrystalline silicon thing 32 produces electric connection adjacent word line.Also there is in polysilicon lines 30 hole 47.

Fig. 8 shows the some processes generalized section of manufacture one storage device, and display via by Fig. 7 polysilicon lines oxidation form silicon oxide line, in having on suitable shape lower surface multiple ridge shape lamination.Polysilicon lines oxidation formed in the oxidation technology of silicon oxide line, residual polycrystalline silicon thing 32 also can be oxidized.

This polysilicon lines 30 and 31 along shape is partially oxidized.This is oxidized along the surface that the relative both sides of the polysilicon lines 30 of shape are exposed, forms silicon oxide line 34 and 35 in these polysilicon lines 36 both sides that narrow.This is oxidized along the surface that the relative both sides of the polysilicon lines 31 of shape are exposed, forms silicon oxide line 37 and 38 similarly in these polysilicon lines 39 both sides that narrow.But, oxide mask 25 and 29 can slow down the oxidation of the top surface of suitable conformal polysilicon line 30 and 31 that covers by this oxide mask 25 and 29.Silicon oxide line 34,35,37 and 38 is formed on the data storage layer that is covered on the rectangular lamination of semi-conducting material along shape, and insert in the raceway groove defined by multiple semiconductor strips lamination.Many silicon oxide lines can be had in other embodiment and be enough to isolate the wordline number accessing this array.Extra silicon oxide line can be formed at along in the Y direction of the turnover page.Because polysilicon expands become silica, the raceway groove 33 between silicon oxide line 35 and 37 can narrow by oxidation so.

An exemplary thickness ranges of silicon oxide line 34,35,37 and 38 is approximately between 400 dusts to 100 dusts.After oxidation, it is approximately between 350 dusts to 100 dusts that this polysilicon lines that narrows has an exemplary thickness ranges.

This example oxidation technology is a furnace oxidation technique, can example horizontal boiler tube, vertical furnace tube or quick thermal treatment process etc. in this way.

Oxidation technology in Fig. 8 solves the problem of the residual polycrystalline silicon shown in subsequent figure.In polysilicon lines, the quantity of material is source limited in this oxidation technology.In this reaction, form silica from the silicon in polysilicon lines and the reaction of oxygen oxygen.Generate silica volume can be the volumetric expansion 120% in silicon source.If represent by percent by volume, if generate the volume 100% of silica, then solid state si+gaseous oxygen of 45% generates the solid oxygen SiClx of 100%.So silicon due to the volumetric expansion that oxidation transformation is silica be approximately 55/45 or 120%.The tiny holes of the outer surface of polysilicon lines 30 and 31 can fill up in this oxidizing process.

Remaining polycrystalline silicon 32 in the figure 7 can become silica 42 when the surface that polysilicon lines 30 is exposed with the relative both sides of 31 is oxidized.Oxidation so can reduce the risk electrically leading the electric connection adjacent word line that bridge causes.Also have a hole 47 in silicon oxide line 34, it is the hole 47 of preexist in polysilicon lines 30.

Polysilicon lines 41 is inserted in raceway groove 33 in Fig. 8.The oxide mask that this polysilicon packed layer is exposed before covering.This filling can use many modes to be formed, and comprises low-pressure chemical vapor deposition process.This fills polysilicon and also inserts among hole 47.

In other examples, if previous process enough well, does not have the doubt of hole 47, because finally packing material can be removed in fig. 12, so also this filling step can be skipped.

Remove unnecessary polysilicon step to be undertaken by many modes, comprise dry method or the wet etching bottom oxide mask to high selectivity, and by cmp.Endpoint detecting can be undertaken by many modes to prevent unnecessary polysilicon to be removed, and comprises spectrochemistry laser analyzer or optics sensing etc.

Oxide mask 25 and 29 is removed and removes further in order to follow-up with the silicon line 36 and 36 of exposed bottom.Removing oxide mask step can be undertaken by many modes, comprises dry etching or such as boric acid (H ₃pO ₄) wet etching its to silicon oxide line 34,35,37 and 38, there is high selectivity, or use many different plasmas etc.

Polysilicon can use the etching mode having a high selectivity relative to silica or silicon nitride to etch.Although be use the etch process with high selectivity to etch, be such as that exposed oxide layer and the exposed nitride of outer oxide 22 still can be lost in this etch process.Loss so can change to some extent along with its position.For example, can be different in the quantity of the oxide loss of the upper surface of silicon oxide line 34,35,37 and 38 and the side surface of outer oxide 22.

The silicon oxide line 34,35,37 and 38 of previous steps is separated by the wordline raceway groove of high-aspect-ratio, and indicates the word line position that will be formed at future steps.The polysilicon 43 residued in hole 47 in fig. 12 can produce the risk electrically leading the electric connection adjacent word line that bridge causes.This polysilicon 43 problem residued in hole 47 can be discussed in Fig. 10.

Figure 13, except discussing, also can discuss removing of polysilicon and removing of outer oxide 22.

Remaining polycrystalline silicon 43 is oxidized to silica 49.Hole can be filled because of its volumetric expansion when polysilicon oxidation.After oxidation, hole 47 is filled with silica, and the silica of this new growth perhaps excessively can fill hole 47 (not shown).

This sacrifice outer oxide perhaps in polysilicon lines 30 photoetching process in figure 6 when etch process arrive at this this sacrifice outer oxide time come to harm.

This sacrifices outside silica and removes from the data storage layer of coated multiple ridge shape lamination.For example, the solution that hydrofluoric acid (HF) is base has SiO ₂high etch rates is to the selective etch of the low etch-rate of SiN.Cause selective etch for this reason, although do not have how many silicon nitrides to silica over etching is etched.The example scope of over etching is 20 ~ 50%.For example, if will remove the silica of 100 dusts, and hydrofluoric acid (HF) etch-rate is 100 dust/10 minute, being then soaked in hydrofluoric acid (HF) 12 minutes is 20% over etching.This additional etches time is 12-10=2 minute, and 2/10=20% over etching.Another kind of selective etching liquid is aqua ammonia (NH ₄oH).After outside silica 22 is sacrificed in removing, silicon nitride layer 21 is exposed.

After oxide removal, an exemplary thickness ranges of silicon oxide line 34,35,37 and 38 is approximately 100 ~ 350 dusts, and having an example is approximately 300 dusts.

In this oxidation, silicon nitride+oxygen (high temperature) forms silica (solid)+nitrogen (gas).The example of high temperature be 1200 DEG C with oxidized silicon nitride, it is 900 DEG C higher of the high temperature compared with silica.Such as OH ^-and O ₂the stronger oxidant of oxygen atom helps oxidized silicon nitride.

In this auto-alignment technique, the silicon nitride of silica in the wordline raceway groove between adjacent oxygen silicon silicon line is formed.The silicon nitride layer 21 of a part is consumed and leaves thinner silicon nitride layer 23.And the silicon oxide layer 24 grown.

Figure 16 shows the some processes generalized section of manufacture one storage device, and display is carried out polysilicon and is filled in exposed surface, and be filled in separately separate silicon oxide line 34,35,37 and 38 shown in Figure 15 wordline raceway groove in.

Polysilicon lines 58,59,61 and 63 along shape is formed on the data storage layer of coated multiple semiconductor strips lamination.These polysilicon lines 58,59,61 and 63 are filled in the gap between multiple semiconductor strips lamination.Extra polysilicon lines can be formed at along in the Y direction of the turnover page.Adjacent polysilicon lines is separated by silicon oxide line.This technique is two mosaic crafts, and polysilicon word line is received in the raceway groove previously defined, be such as between adiacent silica line 34,35, raceway groove between 37 and 38.

Remove unnecessary polysilicon step to be undertaken by many modes, comprise dry etching or wet etching its to bottom oxide mask, and to be removed by cmp.Endpoint detecting can be undertaken by many modes to prevent unnecessary polysilicon to be removed, and comprises spectrochemistry laser analyzer or optics sensing etc.

The side of the rectangular semi-conducting material 11,13,15 of plotted point region on lamination of this polysilicon word line 58,59,61 and 63 definition one multiple tier array and polysilicon word line 50.This mosaic craft is that to remove be such as an alternative techniques of the interconnect shown in Fig. 1, and wherein deposited polysilicon word line is patterned by etching.

Wordline line 58,59,61 and 63 can be use identical or different conductivity (the p+ polysilicon of such as dense doping) with rectangular semi-conducting material 11,13,15.

Therefore, this memory cell comprising field-effect transistor has charge storing structure and is formed in the three-dimensional matrix structure of this plotted point.Use rectangular semi-conducting material and the conductor thickness of about 25 nanometer scale, and the spacing with ridges lamination is also about 25 nanometer scale, the device with tens of layer (such as 30 layers) can reach million (10 in single-chip ¹²) capacity of position.

In one embodiment, charge capturing storage unit is formed at the confluce of rectangular semi-conducting material 11,13,15 and wordline 58,59,61 and 63.Active charge trapping region be in the both sides of rectangular semi-conducting material 11,13,15 between rectangular semi-conducting material 11,13,15 and wordline 58,59, between 61 and 63.In embodiment described herein, each memory cell be bigrid field-effect transistor have two active charge trapping region be respectively position in the both sides of rectangular semi-conducting material.Electronics flows to sensing amplifier along this rectangular semi-conducting material, and it is used to measure the state that memory cell is chosen in instruction one.

Source/drain region along semiconductor strips material in wordline 58,59,61 and 63 both sides can be " without knot ", and namely the dopant profile of source/drain does not need different from the dopant profile of the passage area under wordline.In the embodiment of this " without knot ", charge-trapping field-effect transistor can have p-type channel design.In addition, in certain embodiments, the mode that the doping of source/drain can utilize auto-alignment to inject after definition wordline is formed.

In alternative embodiments, rectangular semi-conducting material 11,13,15 can use light Doped n-type semiconductor body in the arrangement of " without knot ", what cause formation can operate under depletion-mode buries-channel field effect transistor, and this charge capturing storage unit has nature and is offset to lower critical voltage distribution.

Layer of metal silicide (such as tungsten silicide, cobalt silicide, titanium silicide) 51 is formed at the upper surface of wordline 58.A rapid hot technics (RTP) is being carried out after deposition.

Figure 19 is the alternate embodiment of Figure 18, the some processes generalized section of display manufacture one storage device, and shows the polysilicon removal above the oxide-nitride-oxide data storage layer on multiple ridge shape laminations respective in Figure 17.After removing, vertical polysilicon member 52 is retained in the both sides of ridge shape lamination.

Titanium nitride deposits along shape, passes through afterwards to be such as that etching or cmp remove unnecessary metal after deposits tungsten again.

Unlike Figure 18, after polysilicon etch, a horizontal polycrystalline silicon component can retain, and it connects in the vertical polycrystalline silicon component of multiple ridge shape lamination side.

Metal is deposited on exposed horizontal polycrystalline silicon component.More specifically, titanium nitride is the deposition along shape, and deposits tungsten recycling is such as etching or unnecessary material removes by cmp afterwards.

The silicon nitride layer 23 of nucleus or wordline 58 lower zone be compared with silicon oxide line 34 below silicon nitride layer 21 thinner.Thinner silicon nitride layer 23 is results silicon nitride layer 21 part be oxidized described in Figure 12.The not wish operation that minimizing can be helped to produce because of bending electric field compared with thick silicon nitride layer 21 below silicon oxide line 34.

Figure 23 ~ Figure 25 shows the schematic diagram of different M shape grid.Figure 23 shows the M shape grid in Figure 18.Figure 24 shows the M shape grid in Figure 20.Figure 25 shows the M shape grid in Figure 21.In Figure 24 and Figure 25, the neighbouring surface of respective metal wire 64 and 62 is that to be coated be such as the suitable shape bed course of titanium nitride.By contrast, in Figure 20 and Figure 21, the neighbouring surface of respective metal wire 64 and 62 is that not to be coated be such as the suitable shape bed course of titanium nitride.

This figure is the microscopical profile of tunelling electrons of 8 layers of vertical channel thin-film transistor energy gap engineering polysilicon-oxide-nitride-oxide-silica (BE-SONOS) charge-trapping NAND gate device some.This device utilizes half spacing of 75 nanometers to be formed.Its passage is the N-shaped polysilicon of about 18 nanometer thickness.Do not carry out extra knot to inject and formed without junction structure.Between semiconductor strips, be used for the insulating material of channel isolation is in Z-direction, and the silica of its to be thickness be about 40 nanometers.The grid provided is P+ polysilicon lines.This serial selection and grounding selection device have the passage length longer compared with memory cell.This testing apparatus has 32 wordline, without the NAND gate serial of tying.Because the channel-etch that shown in being formed, structure uses has the shape of inclination, have in the bottom of raceway groove apart from wide silicon line, and the insulating material between fine rule is etched more, so the width of Figure below fine rule is also wider than the width of top fine rule apart from polysilicon.The insulating material of this narrower width and the adjacent channel of more wide degree, cause an all around gate effect can produce favorable influence to the control of this device and performance.But potential shadow effect region then can produce the residual polycrystalline silicon problem do not predicted in the region.Fortunately, in different embodiments, residual polycrystalline silicon thing so is oxidized makes not have residual polycrystalline silicon also can not produce electric connection problem between adjacent word line.

In interlayer dielectric layer shape layer after the top of this array, open interlayer hole example in this way tungsten material fill with is formed contact embolism formed in interlayer hole and extend to the upper surface of grid structure.Upper metal line be patterned to connect such as serial selection line to row decoder circuits.Three-dimensional decoding circuit is set up by the mode in scheming, and uses a wordline, a bit line and a serial selection line SSL to choose memory cell.No. 6906940th, the United States Patent (USP) that title is " PlaneDecodingMethodandDeviceforThreeDimensionalMemories " can be consulted.

Consequently, the SONOS kenel memory cell that configuration is the cubical array of NAND gate flash array can be formed.Source electrode, drain electrode and passage are formed in the rectangular semi-conducting material of silicon, and storage material layer comprises the wordline of the tunnel dielectric layer of silica (O), the electric charge storage layer of silicon nitride (N), the stop dielectric layer of silica (O) and polysilicon (S) grid.

In other examples, this NAND gate memory cell also can use other array configurations.The metal-oxide half field effect transistor kenel of such as nano wire is by providing passage area on wire 111 ~ 114 of nano wire or nano tube structure and also being become this kind of mode by configuration, as the paper " ImpactofaProcessVariationonNanowireandNanotubeDevicePerf ormance " of the people such as Paul, IEEETransactionsonElectronDevice, Vol.54, No.9, on September 11st ~ 13,2007, be incorporated by reference data at this.

Figure 27 is an example with the three-dimensional storage structure of inlaying grid.Three-dimensional NAND gate flash memory structure there is the metal level (lengthwise direction is rectangular parallel with semi-conducting material, and width axes direction is parallel with wordline) of serial selection line and bit line to have lengthwise direction rectangular parallel with semi-conducting material.Insulating material removes to expose extra structure in figure.For example, be removed at rectangular of semi-conducting material, insulating material in ridge shape lamination and between the ridge shape lamination that semi-conducting material is rectangular.

This is multilayer laminated is formed on insulating barrier, and comprises many wire 425-1 ... 425-n-1,425-n ridge shape lamination along shape, and it is as wordline WL _n, WL _n-1... WL ₁.This inlays wordline as described herein.The spacing of an example wordline is 75 nanometers, is the combination of spacing 35 nanometer of 40 nanometer wordline thickness and wordline.Multiple ridge shape lamination comprises rectangular semi-conducting material 412,413,414,415.Rectangular semi-conducting material is in the same plane electrically connected by step structure.

Wordline shown here be with from rear to front by the mode label of 1 to N, it is the memory page of even number.To the page of odd number, be then contrary from rear to front by the mode label of N to 1.

Step structure 412A, 413A, 414A, 415A to be such as the rectangular semi-conducting material terminations of rectangular semi-conducting material 412,413,414,415.As shown in FIG., these step structures 412A, 413A, 414A, 415A is electrically connected to be connected to decoding circuit to choose the plane in array from different bit lines.These step structures 412A, 413A, 414A, 415A can be patterned together when defining multiple ridge shape lamination.

Step structure 402B, 403B, 404B, 405B to be such as the rectangular semi-conducting material terminations of rectangular semi-conducting material 402,403,404,405.As shown in FIG., these step structures 402B, 403B, 404B, 405B is electrically connected to be connected to decoding circuit to choose the plane in array from different bit lines.These step structures 402B, 403B, 404B, 405B can be patterned together when defining multiple ridge shape lamination.

Any given rectangular semi-conducting material lamination can couple with step structure 412A, 413A, 414A, 415A or 402B, one of 403B, 404B, 405B, but can not couple with both simultaneously.Rectangular semi-conducting material lamination has one of two kinds of contrary directions: bit line end is to source electrode line extreme direction or source electrode line end to bit line extreme direction.For example, rectangular semi-conducting material lamination 412,413,414,415 has bit line end to source electrode line extreme direction, and rectangular semi-conducting material lamination 402,403,404,405 has source electrode line end to bit line extreme direction.

Rectangular semi-conducting material lamination 412,413,414,415 ends in one end by step structure 412A, 413A, 414A, 415A, by SSL grid structure 419, ground connection selects line GSL426, wordline 425-1 ~ 425-n, ground connection selects line GSL427, and ends in the other end by source electrode line 428.Rectangular semi-conducting material lamination 402,403,404,405 does not arrive step structure 412A, 413A, 414A, 415A.

Rectangular semi-conducting material lamination 402,403,404,405 ends in one end by step structure 402B, 403B, 404B, 405B, by SSL grid structure 409, ground connection selects line GSL427, wordline 425-n ~ 425-1, ground connection selects line GSL426, and ends in the other end by source electrode line (being blocked by other parts).Rectangular semi-conducting material lamination 12,413,414,415 does not arrive step structure 402B, 403B, 404B, 405B.

One deck storage medium is with separating wordline 425-1 to 425-n from rectangular semi-conducting material 412-415 and 402-405 as described mistake before.Ground connection select line GSL426 and 427 be with ridge shape lamination along shape, be similar to wordline.

Each rectangular semi-conducting material lamination ends in one end by step structure, and ends in the other end by source electrode line.For example, rectangular semi-conducting material lamination 412,413,414,415 ends in one end by step structure 412A, 413A, 414A, 415A, and ends in the other end by source electrode line 428.Proximal end in the drawings, a rectangular semi-conducting material lamination ends in one end by step structure 402B, 403B, 404B, 405B, and ends in the other end by another independent source electrode line.And long-range place in the drawings, a rectangular semi-conducting material lamination ends in one end by step structure 412A, 413A, 414A, 415A, and ends in the other end by another independent source electrode line.

Bit line and serial selection line are formed by metal wire ML1, ML2 and ML3.

Transistor is formed between rectangular semi-conducting material 412A, 413A, 414A and wordline 425-1.In these transistors, rectangular semi-conducting material (such as 413) is the passage area as this device.Serial selects SSL grid structure (such as 419,409) to be patterned when defining wordline 425-1 to 425-n simultaneously.One deck silicide is selected to be formed on the upper surface of line 426 and 427 and gate structure 409 and 419 along wordline 425-1 to 425-n and ground connection.Storage material layer 415 can as the gate dielectric layer of transistor.These transistors couple with along the ridge shape lamination in array to choose row as selection grid and decoding circuit.

The first metal layer ML1 comprises serial selection line, and to have lengthwise direction rectangular parallel with semi-conducting material.These ML1 serial selection lines select SSL grid structure to connect by short interlayer hole from different serial.

Second metal level ML2 comprises serial selection line, and to have width axes direction parallel with wordline.These ML2 serial selection lines are connected from different ML1 serial selection line by short interlayer hole.

Generally speaking, these ML1 serial selection lines and ML2 serial selection line allow a string row selection signal to choose the rectangular lamination of a particular semiconductor material.

This first metal layer ML1 also comprises two source electrode lines, and to have width axes direction parallel with wordline.

Finally, the 3rd metal level ML3 comprises bit line to have lengthwise direction rectangular parallel with semi-conducting material.Step structure 412A, 413A, 414A, 415A and 402B, 403B, 404B, 405B of different bit lines and not same order are electrically connected.These ML3 bit lines allow a bit line select signal to choose the rectangular horizontal plane of a particular semiconductor material.

Because particular word line allows a wordline to choose a particular column plane of memory cell, this triple word-line signal, bit line signal and string row selection signal are enough to the particular memory location chosen in three-dimensional memory cell array.

Figure 28 shows in Figure 27 the circuit diagram of the example with the three-dimensional storage structure of inlaying grid.

Show two memory cell planes in figure, each plane has 9 charge capturing storage units and is arranged to NAND gate configuration, and it is the representative illustration of a square, can comprise many planes and many wordline.These two memory cell planes are by the wordline 160,161 as wordline WLn-1, WLn, and it is respectively first, second, and third rectangular semi-conducting material lamination.

First plane of memory cell comprises memory cell 70,71 in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination, and memory cell 73,74 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination, and memory cell 76,77 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination.Each NAND gate serial selects transistor to be connected (such as, grounding selection device 90,72 is connected with the two ends of NAND gate serial 70,71) with a ground connection at two ends.

In this illustrates, the second plane of memory cell is corresponding with cubical baseplane, and comprises the mode that memory cell (such as 80,82 and 84) utilization is similar to the first plane and be arranged in NAND gate serial.

As shown in FIG., wire 161 as wordline WLn comprises vertical stretch and divides, it is corresponding with material in the raceway groove 120 in Fig. 5 between lamination, the memory cell of the interface area in the raceway groove in wordline 161 and all planes between rectangular semi-conducting material (in such as the first plane memory cell 71,74 and 77) to be coupled.

Memory cell string in adjacent laminates is about to bit line end and is exchanged to bit line extreme direction to source electrode line extreme direction and source electrode line end.

Bit line BLn to BLn-196 terminates this memory cell serial, adjoins with serial choice device.For example, at upper memory plane, bit line BLn termination has the memory cell serial of string row selecting transistor 85 and 89.And relative, bit line is not connected with trajectory 88, because bit line end to source electrode line extreme direction is exchanged for source electrode line end to bit line extreme direction by adjacent lamination serial.So in this serial, the other end of corresponding bit line serial therewith connects.At lower memory plane, bit line BLn-1 this memory cell serial that terminates has corresponding string row selecting transistor.

In this arranges, string row selecting transistor 85 is connected with 89 between respective NAND gate serial selection line SSLn-1 and SSLn.Similarly, in this arranges, the similar string row selecting transistor in this cube baseplane connects between respective NAND gate serial selection line SSLn-1 and SSLn.Serial selection line 106 and 108 is connected to different ridges, goes here and there the grid of row selecting transistor to each memory cell serial, and in this example, provide string row selection signal SSLn-1, SSLn and SSLn+1.

On the contrary, row selecting transistor of going here and there is not connected with trajectory 88, because bit line end to source electrode line extreme direction is exchanged for source electrode line end to bit line extreme direction by adjacent lamination serial.So in this serial, the other end of corresponding bit line serial therewith connects.The NAND gate serial with memory cell 73,74 also has respective serial choice device (not shown) in the other end of this serial.Trajectory 88 is terminated by one source pole line 107.

Ground connection selects GSL transistor 90 ~ 95 to be arranged in the first end of this NAND gate serial.Ground connection selects GSL transistor 72,75,78 and the ground connection of the second plane to select corresponding its of GSL transistor to be arranged in the second end of this NAND gate serial.Therefore, ground connection selects GSL transistor to be at the two ends of this NAND gate serial.Store specific one end of serial according to this, this ground connection selects GSL transistor this is stored serial and one source pole line or couples to serial choice device and bit line.

This ground connection selects GSL signal (odd number) 159 and ground connection to select GSL signal (even number) 162 to be at wordline 160,161 opposite side as wordline WLn-1, WLn.In this example, ground connection selects GSL signal (odd number) 159 to be select the grid of GSL transistor 90 ~ 95 to couple with ground connection, and can use and implement with wordline 160,161 identical modes.Similarly, in this example, ground connection selects GSL signal (even number) 162 to select the ground connection of GSL transistor 72,75,78 and the second corresponding plane to select the grid of GSL transistor to couple with ground connection, and can use and implement with wordline 160,161 identical modes.In certain embodiments, these string row selecting transistors and ground connection select transistor can use the dielectric lamination identical with the gate oxide in memory cell.In other examples, typical gate oxide can be used replace.In addition, passage length and width can adjust the handoff functionality that provides these transistors suitable depending on the needs of design.

This integrated circuit 975 comprises use and has the three-dimensional NAND gate flash array 960 inlaying grid or wordline described herein.One column decoder 961 couples with many wordline 962 along the arrangement of storage array 960 column direction and electrically links up.Row decoder 963 and many serial selection lines 964 along the arrangement of storage array 960 line direction electrically ditch pass to and to read the corresponding stored element stack from array 960 and programming data operates.One plane decoder 958 couples via the multiple planes in bit line 959 therewith array 960.Address is supplied to row decoder 963, column decoder 961 and plane decoder 958 by bus 965.Sensing amplifier in square 966 and data input structure couple via data/address bus 967 and row decoder 963 in this example.Data are supplied to Data In-Line 971 by the input/output end port on integrated circuit 975, or by the data source of other inner/outer of integrated circuit 975, input to the data input structure in square 966.In this illustrative embodiments, other circuit 974 are contained within integrated circuit 975, such as general object processor or specific purposes application circuit, or block combiner is to provide the system single chip supported by NAND gate flash array function.Data, by the sensing amplifier in square 966, via DOL Data Output Line 972, are provided to integrated circuit 975, or are provided to other data terminals of integrated circuit 975 inner/outer.

Controller used in the present embodiment is the use of bias voltage adjustment state machine 969, and the application of the bias voltage adjustment supply voltage being produced by voltage source of supply or square 968 or provide is provided, such as read, programme, wipe, erase verification and program verification voltage.This controller can utilize specific purposes logical circuit and apply, as haveing the knack of known by this those skilled in the art.In alternative embodiments, this controller includes general object processor, and it can make in same integrated circuit, to perform the operation of a computer program and control device.In another embodiment, this controller is combined by specific purposes logical circuit and general object processor.

Figure 30 shows a polysilicon layer, and use+pattern indicates, and covering is such as the rectangular semi-conducting material of rectangular semi-conducting material 112, is connected with serial selection line grid structure 109.Figure 30 shows a top view corresponding with Fig. 6, is before etching polysilicon.In Figure 30 ~ Figure 37, no matter have to help to understand serial selection line grid structure and rectangular semi-conducting material all do not represented and shown by " dotted line point " line interlocked by other layer of covering.In Figure 31, polysilicon is etched.Figure 31 shows a top view corresponding with Fig. 6, and the white space in Figure 31 represents polysilicon and is removed, and it is corresponding with the raceway groove 33 in Fig. 6.

Figure 32 shows a top view corresponding with Fig. 8, is after exposed polysilicon is oxidized.In Figure 32 be such as silicon oxide line and the silicon oxide line 34 in Fig. 8 of silicon oxide line 151,35,37 and 38 corresponding.Oxide mask is not shown in Figure 32.Herein by multiple polysilicon lines short circuit; Adjacent polysilicon between multiple polysilicon lines finally can be removed as shown in Figure 36.

Figure 33 shows a top view corresponding with Fig. 9 ~ Figure 11, be after Figure 32, carry out raceway groove that polysilicon is filled between silicon oxide line after.The polysilicon of oxide mask and top capping oxidation silicon line thereof is not shown in Figure 33.

Figure 34 shows a top view corresponding with Figure 12 ~ Figure 13, is to carry out removing after polysilicon fills after Figure 33.Oxide cavity can be filled or be partially filled after polysilicon oxidation.

Figure 35 shows a top view corresponding with Figure 16 ~ Figure 17, carry out removing the outside silica in the oxide-nitride-oxide data storage layer covering rectangular semi-conducting material after Figure 34, and after the outside silica exposed silicon nitride being changed into the oxide-nitride-oxide data storage layer covering rectangular semi-conducting material.Carry out polysilicon and be filled in empty raceway groove between silicon oxide line.Herein by multiple polysilicon lines short circuit; Adjacent polysilicon between multiple polysilicon lines finally can be removed as shown in Figure 36.

Figure 36 shows a top view corresponding with Figure 18, is after by the adjacent polysilicon removal between multiple polysilicon lines and before forming silicide.Also the width that polysilicon structure has variation is shown herein.Be such as wordline 125-1, the wordline of 125-2,125-3 and 125-4 is roughly L shape.This L shape covers a section of rectangular semi-conducting material to be had another section that narrower width L shape is connected with interlayer contact and then has wider width.This larger width is by the additional masks support in an auto-alignment dual resisteance technique.In addition, be such as that ground connection selects some structure of line GSL127 and source electrode line 128 also to have the width wider compared with the narrower section of this wordline.

Figure 37 shows a top view corresponding with Figure 18, is after formation silicide (being shown as oblique line pattern).

Preferred embodiment of the present invention and example disclose as above in detail, but are to be appreciated that above-mentioned example is only as example, are not used to the scope limiting patent.With regard to knowing the personage of this skill, from modifying and combination to correlation technique according to appended claims easily.

Claims

1. form a method for a three-dimensional nonvolatile storage cell array, comprise:

Form more than first line of material on multiple non-volatile memory structural laminate, this more than first line of material is by separate for this more than first line of material by more than first wordline raceway groove;

In this more than first line of material, the structure of multiple partial oxidation is produced by the line of material being oxidized these more than first line of material both sides, the structure of the plurality of partial oxidation comprises many oxide lines and more than first line of material narrowed are bordered on, and the line of material narrowed wherein in these more than first line of material narrowed has the narrower width of line of material in comparatively this more than first line of material;

These more than first line of material narrowed that removing and these many oxide lines are bordered on, to form more than second wordline raceway groove; And

2. method according to claim 1, more comprises:

After removing covers these more than first line of material narrowed of the plurality of non-volatile memory structural laminate, etch the exposed oxide covering the plurality of non-volatile memory structural laminate in this more than second wordline raceway groove; And

Formation oxide covers the plurality of non-volatile memory structural laminate in this more than second wordline raceway groove.

3. method according to claim 1, wherein an oxide line of these many oxide lines has hole, and the method more comprises:

After these more than first line of material narrowed of removing, the retained material at least one wordline raceway groove of this more than second wordline raceway groove is carried out being oxidized to fill this hole at least partly.

4. method according to claim 1, more comprises:

Contain the line of material of these more than first line of material both sides on first and second line of material surface in oxidation package before, form the oxidation mask on the 3rd line of material surface covering this more than first line of material, the 3rd line of material surface is by this first and second line of material surface conjunction.

5. method according to claim 1, wherein forms this more than first line of material and comprises:

Form layer of material on the plurality of non-volatile memory structural laminate, and in this layer material, remove unnecessary material to retain this more than first line of material and form this more than first wordline raceway groove between the line of material that this more than first line of material is adjacent.

6. method according to claim 1, more comprise: before this more than first wordline raceway groove of formation, form the plurality of non-volatile memory structural laminate, the plurality of non-volatile memory structural laminate comprises the multiple rectangular semiconductor separated by insulating material and the charge storing structure be covered on the plurality of rectangular semiconductor.

7. form a method for a three-dimensional nonvolatile storage cell array, comprise:

Form the silicon line of multiple partial oxidation on multiple non-volatile memory structural laminate, the silicon line of the plurality of partial oxidation has multiple unoxidized silicon line in the mid portion of the silicon line of the plurality of partial oxidation and the line of multiple oxidation in the Outboard Sections of the silicon line of the plurality of partial oxidation;

By the plurality of unoxidized silicon line of the mid portion of the silicon line from multiple partial oxidation removing, and retain the line of the plurality of oxidation of Outboard Sections of silicon line of the plurality of partial oxidation, and form multiple wordline raceway groove among the silicon line of the plurality of partial oxidation; And

8. method according to claim 7, more comprises:

After removing covers the plurality of unoxidized silicon line of the plurality of non-volatile memory structural laminate, etch the exposed oxide covering the plurality of non-volatile memory structural laminate in more than second wordline raceway groove; And

Formation oxide covers the plurality of non-volatile memory structural laminate in the plurality of wordline raceway groove.

9. method according to claim 7, more comprises:

By two exposed surface oxidations of silicon line in these many silicon lines.

10. there is an integrated circuit for three-dimensional nonvolatile storage cell array, comprise:

The wordline of many double patternings;

These many wordline of many silicon oxide line separating adjacents;

Multiple non-volatile memory structural laminate is in this cubical array, the plurality of non-volatile memory structural laminate is covered by these many wordline and this many silicon oxide lines, the plurality of non-volatile memory structural laminate comprises a silicon nitride layer, the plurality of non-volatile memory structural laminate comprises a Part I and to be covered by these many wordline and a Part II is covered by these many silicon oxide lines, and this silicon nitride layer in this Part I has the less thickness of this silicon nitride layer in comparatively this Part II.