JP2005286126A5 - - Google Patents

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Publication number
JP2005286126A5
JP2005286126A5 JP2004098440A JP2004098440A JP2005286126A5 JP 2005286126 A5 JP2005286126 A5 JP 2005286126A5 JP 2004098440 A JP2004098440 A JP 2004098440A JP 2004098440 A JP2004098440 A JP 2004098440A JP 2005286126 A5 JP2005286126 A5 JP 2005286126A5
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JP
Japan
Prior art keywords
chip
semiconductor
main surface
semiconductor device
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004098440A
Other languages
English (en)
Japanese (ja)
Other versions
JP4538830B2 (ja
JP2005286126A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2004098440A priority Critical patent/JP4538830B2/ja
Priority claimed from JP2004098440A external-priority patent/JP4538830B2/ja
Priority to US11/049,993 priority patent/US7355272B2/en
Publication of JP2005286126A publication Critical patent/JP2005286126A/ja
Publication of JP2005286126A5 publication Critical patent/JP2005286126A5/ja
Application granted granted Critical
Publication of JP4538830B2 publication Critical patent/JP4538830B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004098440A 2004-03-30 2004-03-30 半導体装置 Expired - Fee Related JP4538830B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004098440A JP4538830B2 (ja) 2004-03-30 2004-03-30 半導体装置
US11/049,993 US7355272B2 (en) 2004-03-30 2005-02-04 Semiconductor device with stacked semiconductor chips of the same type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004098440A JP4538830B2 (ja) 2004-03-30 2004-03-30 半導体装置

Publications (3)

Publication Number Publication Date
JP2005286126A JP2005286126A (ja) 2005-10-13
JP2005286126A5 true JP2005286126A5 (enExample) 2007-05-24
JP4538830B2 JP4538830B2 (ja) 2010-09-08

Family

ID=35095439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004098440A Expired - Fee Related JP4538830B2 (ja) 2004-03-30 2004-03-30 半導体装置

Country Status (2)

Country Link
US (1) US7355272B2 (enExample)
JP (1) JP4538830B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004179442A (ja) * 2002-11-28 2004-06-24 Renesas Technology Corp マルチチップモジュール
JP2007142128A (ja) * 2005-11-18 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
JP4900661B2 (ja) * 2006-02-22 2012-03-21 ルネサスエレクトロニクス株式会社 不揮発性記憶装置
JP2008166430A (ja) 2006-12-27 2008-07-17 Toshiba Microelectronics Corp 半導体装置
US7872340B2 (en) * 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
JP5183186B2 (ja) 2007-12-14 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
JP2011249582A (ja) * 2010-05-27 2011-12-08 Elpida Memory Inc 半導体装置
US8697457B1 (en) 2011-06-22 2014-04-15 Bae Systems Information And Electronic Systems Integration Inc. Devices and methods for stacking individually tested devices to form multi-chip electronic modules
KR20130019290A (ko) * 2011-08-16 2013-02-26 삼성전자주식회사 유니버설 인쇄 회로 기판 및 그것을 포함하는 메모리 카드
CN103681639B (zh) * 2012-09-25 2017-02-08 格科微电子（上海）有限公司 系统级封装结构及其封装方法
TWI747308B (zh) 2019-06-14 2021-11-21 日商索尼半導體解決方案公司 半導體裝置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2670322B1 (fr) 1990-12-05 1997-07-04 Matra Espace Modules de memoire a l'etat solide et dispositifs de memoire comportant de tels modules
JPH06177322A (ja) * 1992-12-04 1994-06-24 Matsushita Electric Ind Co Ltd メモリ素子
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JPH11354713A (ja) * 1998-06-05 1999-12-24 Sony Corp 半導体装置及び実装方法
JP2000164796A (ja) * 1998-11-27 2000-06-16 Nec Corp マルチチップモジュール
JP3581086B2 (ja) * 2000-09-07 2004-10-27 松下電器産業株式会社 半導体装置
JP3744825B2 (ja) * 2000-09-08 2006-02-15 セイコーエプソン株式会社 半導体装置
JP2002237566A (ja) * 2001-02-09 2002-08-23 Matsushita Electric Ind Co Ltd 半導体装置の３次元実装構造体とその製造方法
JP2002280516A (ja) * 2001-03-19 2002-09-27 Toshiba Corp 半導体モジュール
JP3839323B2 (ja) * 2001-04-06 2006-11-01 株式会社ルネサステクノロジ 半導体装置の製造方法
KR100868419B1 (ko) 2001-06-07 2008-11-11 가부시끼가이샤 르네사스 테크놀로지 반도체장치 및 그 제조방법
JP4126891B2 (ja) * 2001-08-03 2008-07-30 セイコーエプソン株式会社 半導体装置の製造方法
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
JP3558070B2 (ja) * 2002-06-05 2004-08-25 松下電器産業株式会社 半導体装置およびその製造方法
TW556961U (en) * 2002-12-31 2003-10-01 Advanced Semiconductor Eng Multi-chip stack flip-chip package
TW588446B (en) * 2003-03-21 2004-05-21 Advanced Semiconductor Eng Multi-chips stacked package
JP4381779B2 (ja) * 2003-11-17 2009-12-09 株式会社ルネサステクノロジ マルチチップモジュール
JP4260617B2 (ja) * 2003-12-24 2009-04-30 株式会社ルネサステクノロジ 半導体装置の製造方法
US20050173807A1 (en) * 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device

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