JP2007149977A5 - - Google Patents

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Publication number
JP2007149977A5
JP2007149977A5 JP2005342479A JP2005342479A JP2007149977A5 JP 2007149977 A5 JP2007149977 A5 JP 2007149977A5 JP 2005342479 A JP2005342479 A JP 2005342479A JP 2005342479 A JP2005342479 A JP 2005342479A JP 2007149977 A5 JP2007149977 A5 JP 2007149977A5
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JP
Japan
Prior art keywords
surface side
output
input
wiring layer
side wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005342479A
Other languages
English (en)
Japanese (ja)
Other versions
JP4906047B2 (ja
JP2007149977A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2005342479A priority Critical patent/JP4906047B2/ja
Priority claimed from JP2005342479A external-priority patent/JP4906047B2/ja
Priority to KR1020060117069A priority patent/KR101277381B1/ko
Priority to US11/563,312 priority patent/US7800214B2/en
Publication of JP2007149977A publication Critical patent/JP2007149977A/ja
Publication of JP2007149977A5 publication Critical patent/JP2007149977A5/ja
Priority to US12/860,415 priority patent/US7888788B2/en
Application granted granted Critical
Publication of JP4906047B2 publication Critical patent/JP4906047B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2005342479A 2005-11-28 2005-11-28 半導体装置 Expired - Fee Related JP4906047B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置
KR1020060117069A KR101277381B1 (ko) 2005-11-28 2006-11-24 반도체 장치
US11/563,312 US7800214B2 (en) 2005-11-28 2006-11-27 Semiconductor device
US12/860,415 US7888788B2 (en) 2005-11-28 2010-08-20 Semiconductor device with reduced cross talk

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2007149977A JP2007149977A (ja) 2007-06-14
JP2007149977A5 true JP2007149977A5 (enExample) 2009-01-22
JP4906047B2 JP4906047B2 (ja) 2012-03-28

Family

ID=38086644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005342479A Expired - Fee Related JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Country Status (3)

Country Link
US (2) US7800214B2 (enExample)
JP (1) JP4906047B2 (enExample)
KR (1) KR101277381B1 (enExample)

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US8386229B1 (en) * 2009-04-17 2013-02-26 Xilinx, Inc. Integrated circuit package component and ball grid array simulation model
JP5405283B2 (ja) * 2009-12-10 2014-02-05 シャープ株式会社 半導体装置およびその電力供給方法
US8891246B2 (en) * 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
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EP2764544A1 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
KR20140085497A (ko) 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
JP2014528652A (ja) 2011-10-03 2014-10-27 インヴェンサス・コーポレイション パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
KR20140073559A (ko) * 2011-10-03 2014-06-16 인벤사스 코포레이션 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화
WO2013052347A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Memory module in a package and its pin configuration
US8629545B2 (en) 2011-10-03 2014-01-14 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
WO2013052411A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
CN103137210A (zh) * 2011-11-23 2013-06-05 鸿富锦精密工业（深圳）有限公司 Ddr信号测试辅助治具
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
JP2015153808A (ja) * 2014-02-12 2015-08-24 ソニー株式会社 半導体チップ、および、半導体モジュール
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
JP6527420B2 (ja) * 2015-07-31 2019-06-05 ルネサスエレクトロニクス株式会社 半導体装置
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
JP6599813B2 (ja) 2016-04-12 2019-10-30 三重富士通セミコンダクター株式会社 半導体集積回路及び半導体集積回路の設計方法
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US9842181B1 (en) * 2016-05-24 2017-12-12 Altera Corporation Method to optimize general-purpose input/output interface pad assignments for integrated circuit
KR102639101B1 (ko) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 전자기간섭 차폐 구조를 갖는 반도체 패키지
JP6402217B2 (ja) * 2017-03-15 2018-10-10 アオイ電子株式会社 半導体装置および半導体装置の製造方法
US10314163B2 (en) * 2017-05-17 2019-06-04 Xilinx, Inc. Low crosstalk vertical connection interface
KR102449619B1 (ko) 2017-12-14 2022-09-30 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 모듈
CN109411436B (zh) * 2018-09-05 2021-04-30 湖北三江航天险峰电子信息有限公司 一种64路模拟量采集bga封装芯片
US11670578B2 (en) 2020-06-02 2023-06-06 Micron Technology, Inc. Ball grid arrays and associated apparatuses and systems
CN115705959B (zh) * 2021-08-17 2024-09-10 比亚迪股份有限公司 母线电容及汽车

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US7791210B2 (en) * 2003-11-05 2010-09-07 Lsi Corporation Semiconductor package having discrete non-active electrical components incorporated into the package
JP4671261B2 (ja) * 2003-11-14 2011-04-13 ルネサスエレクトロニクス株式会社 半導体装置
JP4647243B2 (ja) * 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置

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