JP4906047B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4906047B2
JP4906047B2 JP2005342479A JP2005342479A JP4906047B2 JP 4906047 B2 JP4906047 B2 JP 4906047B2 JP 2005342479 A JP2005342479 A JP 2005342479A JP 2005342479 A JP2005342479 A JP 2005342479A JP 4906047 B2 JP4906047 B2 JP 4906047B2
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JP
Japan
Prior art keywords
output
input
wiring layer
power supply
surface side
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Expired - Fee Related
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JP2005342479A
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English (en)
Japanese (ja)
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JP2007149977A (ja
JP2007149977A5 (enExample
Inventor
泰弘 吉川
元大 諏訪
博 豊嶋
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005342479A priority Critical patent/JP4906047B2/ja
Priority to KR1020060117069A priority patent/KR101277381B1/ko
Priority to US11/563,312 priority patent/US7800214B2/en
Publication of JP2007149977A publication Critical patent/JP2007149977A/ja
Publication of JP2007149977A5 publication Critical patent/JP2007149977A5/ja
Priority to US12/860,415 priority patent/US7888788B2/en
Application granted granted Critical
Publication of JP4906047B2 publication Critical patent/JP4906047B2/ja
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    • H10W70/60—
    • H10W20/43—
    • H10W70/65—
    • H10W72/00—
    • H10W72/90—
    • H10W72/9415—
    • H10W90/724—

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP2005342479A 2005-11-28 2005-11-28 半導体装置 Expired - Fee Related JP4906047B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置
KR1020060117069A KR101277381B1 (ko) 2005-11-28 2006-11-24 반도체 장치
US11/563,312 US7800214B2 (en) 2005-11-28 2006-11-27 Semiconductor device
US12/860,415 US7888788B2 (en) 2005-11-28 2010-08-20 Semiconductor device with reduced cross talk

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2007149977A JP2007149977A (ja) 2007-06-14
JP2007149977A5 JP2007149977A5 (enExample) 2009-01-22
JP4906047B2 true JP4906047B2 (ja) 2012-03-28

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Family Applications (1)

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JP2005342479A Expired - Fee Related JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Country Status (3)

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US (2) US7800214B2 (enExample)
JP (1) JP4906047B2 (enExample)
KR (1) KR101277381B1 (enExample)

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JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
JP4638902B2 (ja) 2007-09-27 2011-02-23 Ｏｋｉセミコンダクタ株式会社 半導体素子、及びそのレイアウト方法
JP4645635B2 (ja) * 2007-11-02 2011-03-09 セイコーエプソン株式会社 電子部品
JP2010093109A (ja) * 2008-10-09 2010-04-22 Renesas Technology Corp 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法
US8386229B1 (en) * 2009-04-17 2013-02-26 Xilinx, Inc. Integrated circuit package component and ball grid array simulation model
JP5405283B2 (ja) * 2009-12-10 2014-02-05 シャープ株式会社 半導体装置およびその電力供給方法
US8891246B2 (en) * 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
EP2769409A1 (en) 2011-10-03 2014-08-27 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
KR101894823B1 (ko) 2011-10-03 2018-09-04 인벤사스 코포레이션 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화
WO2013052321A2 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
WO2013052544A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization with terminal grids offset from center of package
WO2013052411A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659143B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
WO2013052345A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
WO2013052323A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
CN103137210A (zh) * 2011-11-23 2013-06-05 鸿富锦精密工业（深圳）有限公司 Ddr信号测试辅助治具
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
JP2015153808A (ja) * 2014-02-12 2015-08-24 ソニー株式会社 半導体チップ、および、半導体モジュール
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
JP6527420B2 (ja) * 2015-07-31 2019-06-05 ルネサスエレクトロニクス株式会社 半導体装置
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
JP6599813B2 (ja) 2016-04-12 2019-10-30 三重富士通セミコンダクター株式会社 半導体集積回路及び半導体集積回路の設計方法
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US9842181B1 (en) * 2016-05-24 2017-12-12 Altera Corporation Method to optimize general-purpose input/output interface pad assignments for integrated circuit
KR102639101B1 (ko) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 전자기간섭 차폐 구조를 갖는 반도체 패키지
JP6402217B2 (ja) * 2017-03-15 2018-10-10 アオイ電子株式会社 半導体装置および半導体装置の製造方法
US10314163B2 (en) * 2017-05-17 2019-06-04 Xilinx, Inc. Low crosstalk vertical connection interface
KR102449619B1 (ko) 2017-12-14 2022-09-30 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 모듈
CN109411436B (zh) * 2018-09-05 2021-04-30 湖北三江航天险峰电子信息有限公司 一种64路模拟量采集bga封装芯片
US11670578B2 (en) * 2020-06-02 2023-06-06 Micron Technology, Inc. Ball grid arrays and associated apparatuses and systems
CN115705959B (zh) * 2021-08-17 2024-09-10 比亚迪股份有限公司 母线电容及汽车

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JPH11135668A (ja) 1997-10-31 1999-05-21 Nec Corp 半導体装置
US6008534A (en) * 1998-01-14 1999-12-28 Lsi Logic Corporation Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
JP2001044591A (ja) * 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd 配線基板
JP2001203298A (ja) 2000-01-19 2001-07-27 Hitachi Ltd 半導体装置およびその製造方法
TW577152B (en) * 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
JP2002222892A (ja) * 2001-01-26 2002-08-09 Kyocera Corp 多層配線基板
US6800947B2 (en) * 2001-06-27 2004-10-05 Intel Corporation Flexible tape electronics packaging
JP4079699B2 (ja) * 2001-09-28 2008-04-23 富士通株式会社 多層配線回路基板
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
JP4211378B2 (ja) * 2002-12-13 2009-01-21 ソニー株式会社 キャパシタ素子
US7791210B2 (en) * 2003-11-05 2010-09-07 Lsi Corporation Semiconductor package having discrete non-active electrical components incorporated into the package
JP4671261B2 (ja) * 2003-11-14 2011-04-13 ルネサスエレクトロニクス株式会社 半導体装置
JP4647243B2 (ja) * 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
KR20070055959A (ko) 2007-05-31
US7888788B2 (en) 2011-02-15
US20070120245A1 (en) 2007-05-31
JP2007149977A (ja) 2007-06-14
KR101277381B1 (ko) 2013-06-20
US7800214B2 (en) 2010-09-21
US20100314761A1 (en) 2010-12-16

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