JP4906047B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4906047B2
JP4906047B2 JP2005342479A JP2005342479A JP4906047B2 JP 4906047 B2 JP4906047 B2 JP 4906047B2 JP 2005342479 A JP2005342479 A JP 2005342479A JP 2005342479 A JP2005342479 A JP 2005342479A JP 4906047 B2 JP4906047 B2 JP 4906047B2
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JP
Japan
Prior art keywords
output
input
wiring layer
power supply
surface side
Prior art date
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Expired - Fee Related
Application number
JP2005342479A
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English (en)
Japanese (ja)
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JP2007149977A5 (enExample
JP2007149977A (ja
Inventor
泰弘 吉川
元大 諏訪
博 豊嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005342479A priority Critical patent/JP4906047B2/ja
Priority to KR1020060117069A priority patent/KR101277381B1/ko
Priority to US11/563,312 priority patent/US7800214B2/en
Publication of JP2007149977A publication Critical patent/JP2007149977A/ja
Publication of JP2007149977A5 publication Critical patent/JP2007149977A5/ja
Priority to US12/860,415 priority patent/US7888788B2/en
Application granted granted Critical
Publication of JP4906047B2 publication Critical patent/JP4906047B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP2005342479A 2005-11-28 2005-11-28 半導体装置 Expired - Fee Related JP4906047B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置
KR1020060117069A KR101277381B1 (ko) 2005-11-28 2006-11-24 반도체 장치
US11/563,312 US7800214B2 (en) 2005-11-28 2006-11-27 Semiconductor device
US12/860,415 US7888788B2 (en) 2005-11-28 2010-08-20 Semiconductor device with reduced cross talk

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005342479A JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2007149977A JP2007149977A (ja) 2007-06-14
JP2007149977A5 JP2007149977A5 (enExample) 2009-01-22
JP4906047B2 true JP4906047B2 (ja) 2012-03-28

Family

ID=38086644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005342479A Expired - Fee Related JP4906047B2 (ja) 2005-11-28 2005-11-28 半導体装置

Country Status (3)

Country Link
US (2) US7800214B2 (enExample)
JP (1) JP4906047B2 (enExample)
KR (1) KR101277381B1 (enExample)

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JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
JP4638902B2 (ja) 2007-09-27 2011-02-23 Ｏｋｉセミコンダクタ株式会社 半導体素子、及びそのレイアウト方法
JP4645635B2 (ja) * 2007-11-02 2011-03-09 セイコーエプソン株式会社 電子部品
JP2010093109A (ja) * 2008-10-09 2010-04-22 Renesas Technology Corp 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法
US8386229B1 (en) * 2009-04-17 2013-02-26 Xilinx, Inc. Integrated circuit package component and ball grid array simulation model
JP5405283B2 (ja) * 2009-12-10 2014-02-05 シャープ株式会社 半導体装置およびその電力供給方法
US8891246B2 (en) * 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
WO2013052323A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
EP2764544A1 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
KR20140085497A (ko) 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
JP2014528652A (ja) 2011-10-03 2014-10-27 インヴェンサス・コーポレイション パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
KR20140073559A (ko) * 2011-10-03 2014-06-16 인벤사스 코포레이션 패키지 기판으로의 와이어 본드 없이 어셈블리에서 신호 단자의 복제 세트를 이용한 스터브 최소화
WO2013052347A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Memory module in a package and its pin configuration
US8629545B2 (en) 2011-10-03 2014-01-14 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
WO2013052411A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
CN103137210A (zh) * 2011-11-23 2013-06-05 鸿富锦精密工业（深圳）有限公司 Ddr信号测试辅助治具
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
JP2015153808A (ja) * 2014-02-12 2015-08-24 ソニー株式会社 半導体チップ、および、半導体モジュール
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
JP6527420B2 (ja) * 2015-07-31 2019-06-05 ルネサスエレクトロニクス株式会社 半導体装置
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
JP6599813B2 (ja) 2016-04-12 2019-10-30 三重富士通セミコンダクター株式会社 半導体集積回路及び半導体集積回路の設計方法
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US9842181B1 (en) * 2016-05-24 2017-12-12 Altera Corporation Method to optimize general-purpose input/output interface pad assignments for integrated circuit
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JP6402217B2 (ja) * 2017-03-15 2018-10-10 アオイ電子株式会社 半導体装置および半導体装置の製造方法
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CN109411436B (zh) * 2018-09-05 2021-04-30 湖北三江航天险峰电子信息有限公司 一种64路模拟量采集bga封装芯片
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JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
KR20070055959A (ko) 2007-05-31
JP2007149977A (ja) 2007-06-14
US7800214B2 (en) 2010-09-21
US20100314761A1 (en) 2010-12-16
KR101277381B1 (ko) 2013-06-20
US20070120245A1 (en) 2007-05-31
US7888788B2 (en) 2011-02-15

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