JP2005167197A - ウエハ及び半導体装置並びにこれらの製造方法 - Google Patents
ウエハ及び半導体装置並びにこれらの製造方法 Download PDFInfo
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
【解決手段】 絶縁性基板201上に、単結晶シリコン集積回路61…が形成される。上記単結晶シリコン集積回路61は、周囲全方向が酸化物(BOX層43、二酸化珪素50、54、57)によって囲まれた構造となっている。
【選択図】 図6
Description
本発明の一実施の形態について説明すれば、以下の通りである。
本発明の別の実施の形態について説明すれば、以下の通りである。
2 シリコン層
3 BOX層(酸化物)
4 活性層
5 溝
6 溝
9 二酸化珪素(酸化物)
10 二酸化珪素(酸化物)
11 ゲート酸化膜
12 ゲート電極
13 層間絶縁膜(酸化物)
21 単結晶シリコン集積回路
31 非単結晶シリコントランジスタ
41 SOIウエハ
42 シリコン層
43 BOX層
44 活性層
45 溝
46 溝
50 二酸化珪素(酸化物)
51 ゲート酸化膜
52 ゲート電極
53 ソース・ドレイン
54 層間絶縁膜(酸化物)
55 コンタクト
56 メタル配線
57 層間絶縁膜(酸化物)
58 第2のコンタクト
59 第2のメタル配線
61 単結晶シリコン集積回路
71 非単結晶シリコントランジスタ
101 絶縁性基板
102 酸化膜
201 絶縁性基板
202 酸化膜
Claims (15)
- シリコン基板に形成された埋め込み酸化膜層上のシリコン活性層に所望数の単結晶シリコン集積回路が形成され、
上記単結晶シリコン集積回路表面が酸化物で覆われると共に、該単結晶シリコン集積回路間及び該単結晶シリコン集積回路内の素子間に、上記埋め込み酸化膜層に達する深さまで酸化物が充填されていることを特徴とするウエハ。 - 上記酸化物は、上記埋め込み酸化膜層と同じ材料からなることを特徴とする請求項1に記載のウエハ。
- シリコン基板に埋め込み酸化膜層を形成し、該埋め込み酸化膜層上のシリコン活性層に所望数の単結晶シリコン集積回路を形成し、上記単結晶シリコン集積回路間及び該単結晶シリコン集積回路内の素子間を酸化物によって同時に分離すると共に、単結晶シリコン集積回路表面を酸化物で覆うことを特徴とするウエハの製造方法。
- シリコン基板に埋め込み酸化膜層を形成し、該埋め込み酸化膜層上のシリコン活性層に所望数の単結晶シリコン集積回路を形成し、上記単結晶シリコン集積回路間の集積回路分離領域及び該単結晶シリコン集積回路内の素子間の素子分離領域に、上記埋め込み酸化膜層にまで達する深さの溝を形成し、該溝に酸化物を同時に充填すると共に、単結晶シリコン集積回路表面を酸化物で覆うことを特徴とするウエハの製造方法。
- 絶縁性基板の上に、少なくとも単結晶シリコン集積回路が形成された半導体装置において、
上記単結晶シリコン集積回路は、周囲全方向が酸化物によって囲まれた構造となっていることを特徴とする半導体装置。 - 上記絶縁性基板上には、非単結晶シリコントランジスタが形成されていることを特徴とする請求項5に記載の半導体装置。
- 上記酸化物は、二酸化珪素であることを特徴とする請求項5または6に記載の半導体装置。
- 絶縁性基板の上に、少なくとも単結晶シリコン集積回路が形成された半導体装置の製造方法において、
シリコン基板に埋め込み酸化膜層が設けられた半導体ウエハに、所望数の単結晶シリコン集積回路を形成し、該単結晶シリコン集積回路間及び該単結晶シリコン集積回路内の素子間を酸化物によって同時に分離した後、該半導体ウエハから単結晶シリコン集積回路を上記埋め込み酸化膜層を含めて切り出し、該単結晶シリコン集積回路の埋め込み酸化膜層とは反対側表面と、上記絶縁性基板とを貼り合わせることを特徴とする半導体装置の製造方法。 - 絶縁性基板の上に、少なくとも単結晶シリコン集積回路が形成された半導体装置の製造方法において、
シリコン基板に埋め込み酸化膜層が設けられた半導体ウエハの該埋め込み酸化膜層上のシリコン活性層に、所望数の単結晶シリコン集積回路を形成し、該単結晶シリコン集積回路間の集積回路分離領域及び該単結晶シリコン集積回路内の素子間の素子分離領域に、該埋め込み酸化膜層にまで達する深さの溝を形成し、該溝に酸化物を同時に充填した後、該半導体ウエハから単結晶シリコン集積回路を上記埋め込み酸化膜層を含めて切り出し、該単結晶シリコン集積回路の埋め込み酸化膜層とは反対側表面と、上記絶縁性基板とを貼り合わせることを特徴とする半導体装置の製造方法。 - 単結晶シリコン集積回路を絶縁性基板上に貼り合せた後、熱処理により貼り合せ強度を向上させることを特徴とする請求項8または9に記載の半導体装置の製造方法。
- 単結晶シリコン集積回路を絶縁性基板上に貼り合せ、熱処理を行う前もしくは後に、埋め込み酸化膜層まで薄膜化することを特徴とする請求項8、9又は10に記載の半導体装置の製造方法。
- 上記半導体ウエハから単結晶シリコン集積回路を切り出す前に、上記半導体ウエハを薄層化し、
半導体ウエハを薄膜化した後に切り出しを行った単結晶シリコン集積回路と絶縁性基板とを貼り合わせた後、貼り合せ面側とは反対側を、上記埋め込み酸化膜まで薄膜化することを特徴とする請求項10に記載の半導体装置の製造方法。 - 上記半導体ウエハから単結晶シリコン集積回路を切り出す前に、上記半導体ウエハを研磨及び/又はエッチングによって薄層化することを特徴とする請求項12に記載の半導体装置の製造方法。
- 単結晶シリコン集積回路を絶縁性基板上に作製した後、上記絶縁性基板の単結晶シリコン集積回路の貼り合わせ面側に非単結晶シリコントランジスタを形成することを特徴とする請求項8〜13の何れか1項に記載の半導体装置の製造方法。
- 非単結晶シリコントランジスタを絶縁性基板上に作製した後、上記絶縁性基板上に単結晶シリコン集積回路を作製することを特徴とする請求項8〜13の何れか1項に記載の半導体装置の製造方法。
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JP2004275701A JP4610982B2 (ja) | 2003-11-11 | 2004-09-22 | 半導体装置の製造方法 |
US10/983,686 US7390696B2 (en) | 2003-11-11 | 2004-11-09 | Wafer, semiconductor device, and fabrication methods therefor |
KR1020040091536A KR100732403B1 (ko) | 2003-11-11 | 2004-11-10 | 웨이퍼와 반도체 장치 및 이들의 제조방법 |
EP04257009A EP1531489A3 (en) | 2003-11-11 | 2004-11-11 | Wafer, semiconductor device, and fabrication methods therefor |
US12/073,490 US20080164623A1 (en) | 2003-11-11 | 2008-03-06 | Wafer, semiconductor device, and fabrication methods therefor |
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- 2004-11-10 KR KR1020040091536A patent/KR100732403B1/ko not_active IP Right Cessation
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Cited By (8)
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WO2007111008A1 (ja) * | 2006-03-28 | 2007-10-04 | Sharp Kabushiki Kaisha | 半導体素子の転写方法及び半導体装置の製造方法並びに半導体装置 |
WO2007148448A1 (ja) * | 2006-06-20 | 2007-12-27 | Sharp Kabushiki Kaisha | 半導体装置及びその製造方法 |
JP2008147418A (ja) * | 2006-12-11 | 2008-06-26 | Hitachi Ltd | 薄膜トランジスタ装置、画像表示装置およびその製造方法 |
WO2009084125A1 (ja) * | 2007-12-27 | 2009-07-09 | Sharp Kabushiki Kaisha | 半導体装置の製造方法及び半導体装置 |
US8188564B2 (en) | 2007-12-27 | 2012-05-29 | Sharp Kabushiki Kaisha | Semiconductor device having a planarizing film formed in a region of a step portion |
JP2009177144A (ja) * | 2007-12-28 | 2009-08-06 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法 |
WO2009090780A1 (ja) * | 2008-01-15 | 2009-07-23 | Sharp Kabushiki Kaisha | 半導体装置、その製造方法及び表示装置 |
WO2019159614A1 (ja) * | 2018-02-13 | 2019-08-22 | パナソニックIpマネジメント株式会社 | 無線通信半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1531489A3 (en) | 2007-10-17 |
KR100732403B1 (ko) | 2007-06-27 |
KR20050045893A (ko) | 2005-05-17 |
US20050098827A1 (en) | 2005-05-12 |
US20080164623A1 (en) | 2008-07-10 |
EP1531489A2 (en) | 2005-05-18 |
JP4610982B2 (ja) | 2011-01-12 |
US7390696B2 (en) | 2008-06-24 |
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