JP2004362761A5 - - Google Patents

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Publication number
JP2004362761A5
JP2004362761A5 JP2004166016A JP2004166016A JP2004362761A5 JP 2004362761 A5 JP2004362761 A5 JP 2004362761A5 JP 2004166016 A JP2004166016 A JP 2004166016A JP 2004166016 A JP2004166016 A JP 2004166016A JP 2004362761 A5 JP2004362761 A5 JP 2004362761A5
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JP
Japan
Prior art keywords
memory device
state
semiconductor memory
bit line
control signal
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JP2004166016A
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English (en)
Japanese (ja)
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JP2004362761A (ja
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Priority claimed from KR1020030035564A external-priority patent/KR100546328B1/ko
Priority claimed from US10/773,901 external-priority patent/US7085154B2/en
Application filed filed Critical
Publication of JP2004362761A publication Critical patent/JP2004362761A/ja
Publication of JP2004362761A5 publication Critical patent/JP2004362761A5/ja
Pending legal-status Critical Current

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JP2004166016A 2003-06-03 2004-06-03 半導体メモリ装置及びそのプログラミング方法 Pending JP2004362761A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030035564A KR100546328B1 (ko) 2003-06-03 2003-06-03 상 변화 메모리 장치로 인가되는 펄스 폭 자동 제어 방법및 장치
US10/773,901 US7085154B2 (en) 2003-06-03 2004-02-06 Device and method for pulse width control in a phase change memory device

Publications (2)

Publication Number Publication Date
JP2004362761A JP2004362761A (ja) 2004-12-24
JP2004362761A5 true JP2004362761A5 (https=) 2007-06-14

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ID=36815433

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JP2004166016A Pending JP2004362761A (ja) 2003-06-03 2004-06-03 半導体メモリ装置及びそのプログラミング方法

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US (2) US7085154B2 (https=)
JP (1) JP2004362761A (https=)
CN (1) CN100514492C (https=)
DE (1) DE102004025975B4 (https=)
IT (1) ITMI20041046A1 (https=)

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