ITMI20041046A1 - Dispositivo e procedimento per controllo di larghezza di impulso in un dispositivo di memoria a cambiamento di fase - Google Patents
Dispositivo e procedimento per controllo di larghezza di impulso in un dispositivo di memoria a cambiamento di faseInfo
- Publication number
- ITMI20041046A1 ITMI20041046A1 IT001046A ITMI20041046A ITMI20041046A1 IT MI20041046 A1 ITMI20041046 A1 IT MI20041046A1 IT 001046 A IT001046 A IT 001046A IT MI20041046 A ITMI20041046 A IT MI20041046A IT MI20041046 A1 ITMI20041046 A1 IT MI20041046A1
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- pulse width
- phase change
- change memory
- width control
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
- G11C2013/0066—Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030035564A KR100546328B1 (ko) | 2003-06-03 | 2003-06-03 | 상 변화 메모리 장치로 인가되는 펄스 폭 자동 제어 방법및 장치 |
US10/773,901 US7085154B2 (en) | 2003-06-03 | 2004-02-06 | Device and method for pulse width control in a phase change memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
ITMI20041046A1 true ITMI20041046A1 (it) | 2004-08-25 |
Family
ID=36815433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT001046A ITMI20041046A1 (it) | 2003-06-03 | 2004-05-25 | Dispositivo e procedimento per controllo di larghezza di impulso in un dispositivo di memoria a cambiamento di fase |
Country Status (5)
Country | Link |
---|---|
US (2) | US7085154B2 (it) |
JP (1) | JP2004362761A (it) |
CN (1) | CN100514492C (it) |
DE (1) | DE102004025975B4 (it) |
IT (1) | ITMI20041046A1 (it) |
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-
2004
- 2004-02-06 US US10/773,901 patent/US7085154B2/en not_active Expired - Lifetime
- 2004-05-18 DE DE102004025975A patent/DE102004025975B4/de not_active Expired - Fee Related
- 2004-05-25 IT IT001046A patent/ITMI20041046A1/it unknown
- 2004-06-02 CN CNB2004100465607A patent/CN100514492C/zh not_active Expired - Fee Related
- 2004-06-03 JP JP2004166016A patent/JP2004362761A/ja active Pending
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2006
- 2006-04-18 US US11/405,993 patent/US7180771B2/en not_active Expired - Fee Related
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DE102004025975B4 (de) | 2010-11-11 |
US20060181932A1 (en) | 2006-08-17 |
US7180771B2 (en) | 2007-02-20 |
CN1574093A (zh) | 2005-02-02 |
CN100514492C (zh) | 2009-07-15 |
US7085154B2 (en) | 2006-08-01 |
DE102004025975A1 (de) | 2004-12-30 |
JP2004362761A (ja) | 2004-12-24 |
US20040246804A1 (en) | 2004-12-09 |
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