JP2004362761A - 半導体メモリ装置及びそのプログラミング方法 - Google Patents

半導体メモリ装置及びそのプログラミング方法 Download PDF

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Publication number
JP2004362761A
JP2004362761A JP2004166016A JP2004166016A JP2004362761A JP 2004362761 A JP2004362761 A JP 2004362761A JP 2004166016 A JP2004166016 A JP 2004166016A JP 2004166016 A JP2004166016 A JP 2004166016A JP 2004362761 A JP2004362761 A JP 2004362761A
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Prior art keywords
memory device
state
bit line
control signal
voltage
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JP2004166016A
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Japanese (ja)
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JP2004362761A5 (https=
Inventor
Woo-Yeong Cho
趙佑榮
Kyung-Hee Kim
金敬▲姫▼
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020030035564A external-priority patent/KR100546328B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2004362761A publication Critical patent/JP2004362761A/ja
Publication of JP2004362761A5 publication Critical patent/JP2004362761A5/ja
Pending legal-status Critical Current

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0064Verifying circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • G11C13/0026Bit-line or column circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0061Timing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012Marginal testing, e.g. race, voltage or current testing of timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0064Verifying circuits or methods
    • G11C2013/0066Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/0092Write characterized by the shape, e.g. form, length, amplitude of the write pulse

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
JP2004166016A 2003-06-03 2004-06-03 半導体メモリ装置及びそのプログラミング方法 Pending JP2004362761A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030035564A KR100546328B1 (ko) 2003-06-03 2003-06-03 상 변화 메모리 장치로 인가되는 펄스 폭 자동 제어 방법및 장치
US10/773,901 US7085154B2 (en) 2003-06-03 2004-02-06 Device and method for pulse width control in a phase change memory device

Publications (2)

Publication Number Publication Date
JP2004362761A true JP2004362761A (ja) 2004-12-24
JP2004362761A5 JP2004362761A5 (https=) 2007-06-14

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ID=36815433

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JP2004166016A Pending JP2004362761A (ja) 2003-06-03 2004-06-03 半導体メモリ装置及びそのプログラミング方法

Country Status (5)

Country Link
US (2) US7085154B2 (https=)
JP (1) JP2004362761A (https=)
CN (1) CN100514492C (https=)
DE (1) DE102004025975B4 (https=)
IT (1) ITMI20041046A1 (https=)

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JP2006277822A (ja) * 2005-03-29 2006-10-12 Nec Corp 磁気ランダムアクセスメモリ及びその動作方法
JP2007123908A (ja) * 2005-10-28 2007-05-17 Samsung Electronics Co Ltd 相変化メモリ素子、その動作及び製造方法
JP2007207412A (ja) * 2006-01-03 2007-08-16 Qimonda Ag 抵抗メモリのための書き込み回路
JP2009157982A (ja) * 2007-12-26 2009-07-16 Toshiba Corp 不揮発性半導体記憶装置
US7580277B2 (en) 2005-01-19 2009-08-25 Elpida Memory, Inc. Memory device including a programmable resistance element
JP2010218603A (ja) * 2009-03-13 2010-09-30 Sharp Corp 不揮発性可変抵抗素子のフォーミング処理の制御回路、並びにフォーミング処理の制御方法
JP2011526401A (ja) * 2008-06-27 2011-10-06 サンディスク スリーディー,エルエルシー 不揮発性記憶における同時書込みと検証
JP2011526403A (ja) * 2008-06-27 2011-10-06 サンディスク スリーディー,エルエルシー 不揮発性記憶用の短いリセットパルス
JP2011253595A (ja) * 2010-06-03 2011-12-15 Toshiba Corp 不揮発性半導体記憶装置
JP2012504839A (ja) * 2008-10-06 2012-02-23 サンディスク スリーディー,エルエルシー 可逆的抵抗スイッチングメモリ材料用のセット及びリセット検出回路
US8139404B2 (en) 2009-04-03 2012-03-20 Elpida Memory, Inc. Semiconductor memory device
US8456913B2 (en) 2010-09-03 2013-06-04 SK Hynix Inc. Semiconductor memory apparatus and method for controlling programming current pulse
KR101284527B1 (ko) 2010-09-23 2013-07-16 마이크론 테크놀로지, 인크. 역치 에지 검출을 이용한 상 변화 메모리 상태 판정
JP2014529838A (ja) * 2011-08-18 2014-11-13 マイクロン テクノロジー,インク. 回路においてスナップバック事象を検知するための装置、デバイスおよび方法
US9312003B2 (en) 2013-09-18 2016-04-12 Kabushiki Kaisha Toshiba Semiconductor memory device and method of performing setting operation in semiconductor memory device
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US7159181B2 (en) * 2003-10-01 2007-01-02 Sunrise Medical Hhg Inc. Control system with customizable menu structure for personal mobility vehicle
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TWI288931B (en) 2004-06-19 2007-10-21 Samsung Electronics Co Ltd Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement
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