JP5111883B2 - しきい電圧制御pramのプログラム方法 - Google Patents
しきい電圧制御pramのプログラム方法 Download PDFInfo
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- JP5111883B2 JP5111883B2 JP2007033804A JP2007033804A JP5111883B2 JP 5111883 B2 JP5111883 B2 JP 5111883B2 JP 2007033804 A JP2007033804 A JP 2007033804A JP 2007033804 A JP2007033804 A JP 2007033804A JP 5111883 B2 JP5111883 B2 JP 5111883B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
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- Crystallography & Structural Chemistry (AREA)
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Description
An Access−Transistor−Free (0T/1R) Non−Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self−Rectifying Chalcogenide Device (Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International 8−10 Dec. 2003 Pages:37.4.1 − 37.4.4Z
2 物質層
3 下部電極
Claims (4)
- プログラミングによりカルコゲニド物質の非晶質状態を決定して、ハイデータとロー データに対応するしきい電圧を有するプログラミング領域を形成し、
プログラミング時、プログラミングパルスのトレーリングエッジの時間的制御によってカルコゲニド物質の冷却速度を制御し、これによってカルコゲニド物質のしきい電圧を調節し、
前記カルコゲニド物質が前記ハイデータと前記ローデータに対応するしきい電圧を有するようにプログラミングするための前記プログラミングパルスは、互いに連続する溶融期間と冷却期間を有し、
前記プログラミングパルスの溶融期間は、サイズ及び幅が互いに同じく、
前記プログラミングパルスの冷却期間は、前記カルコゲニド物質の冷却速度が相異なるように互いに異なる幅を有することを特徴とするPRAMのプログラミング方法。 - 前記カルコゲニド物質が前記ハイデータに対応するしきい電圧を有するようにプログラミングするためのプログラミングパルスの冷却期間は、前記カルコゲニド物質が前記ローデータに対応するしきい電圧を有するようにするためのプログラミングパルスの対応する冷却期間に比べて長いことを特徴とする請求項1に記載のPRAMのプログラミング方法。
- 前記カルコゲニド物質が前記ローデータに対応するしきい電圧を有するようにプログラミングするためのプログラミングパルスの冷却期間は0より大きく、20nsがハイであり、前記カルコゲニド物質が前記ハイデータに対応するしきい電圧を有するようにプログラミングするためのプログラミングパルスの冷却期間は、20ns以上より大きいことを特徴とする請求項1に記載のPRAMのプログラミング方法。
- プログラミングによりカルコゲニド物質の非晶質状態を決定してハイデータとローデータに対応するしきい電圧を有するプログラミング領域を形成し、
プログラミング時、プログラミングパルスのトレーリングエッジの時間的制御によりカルコゲニド物質の冷却速度を制御し、これによりカルコゲニド物質のしきい電圧を調節し、
前記ローデータに対応する前記カルコゲニド物質のしきい電圧を有するようにプログラミングするためのプログラミングパルスは溶融期間を有し、
前記ハイデータに対応する前記カルコゲニド物質のしきい電圧を有するようにプログラミングするためのプログラミングパルスは互いに連続する溶融期間と冷却期間を有し、
前記プログラミングパルスの溶融期間はサイズ及び幅が互いに同じであることを特徴とするPRAMのプログラミング方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2006-0015155 | 2006-02-16 | ||
KR20060015155 | 2006-02-16 | ||
KR10-2006-0045815 | 2006-05-22 | ||
KR1020060045815A KR20070082473A (ko) | 2006-02-16 | 2006-05-22 | 문턱 전압제어 pram의 프로그램 방법 |
Publications (2)
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JP2007220281A JP2007220281A (ja) | 2007-08-30 |
JP5111883B2 true JP5111883B2 (ja) | 2013-01-09 |
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Application Number | Title | Priority Date | Filing Date |
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JP2007033804A Active JP5111883B2 (ja) | 2006-02-16 | 2007-02-14 | しきい電圧制御pramのプログラム方法 |
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US (1) | US7626859B2 (ja) |
JP (1) | JP5111883B2 (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
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US7940552B2 (en) * | 2007-04-30 | 2011-05-10 | Samsung Electronics Co., Ltd. | Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices |
KR100914267B1 (ko) * | 2007-06-20 | 2009-08-27 | 삼성전자주식회사 | 가변저항 메모리 장치 및 그것의 형성방법 |
KR101308549B1 (ko) * | 2007-07-12 | 2013-09-13 | 삼성전자주식회사 | 멀티-레벨 상변환 메모리 장치 및 그것의 쓰기 방법 |
US7729163B2 (en) * | 2008-03-26 | 2010-06-01 | Micron Technology, Inc. | Phase change memory |
JP5205662B2 (ja) * | 2008-04-01 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7897955B2 (en) * | 2008-11-03 | 2011-03-01 | Seagate Technology Llc | Programmable resistive memory cell with filament placement structure |
US8116115B2 (en) | 2008-11-06 | 2012-02-14 | Micron Technology, Inc. | Multilevel phase change memory operation |
US8166368B2 (en) * | 2009-02-24 | 2012-04-24 | International Business Machines Corporation | Writing a special symbol to a memory to indicate the absence of a data signal |
US8023345B2 (en) * | 2009-02-24 | 2011-09-20 | International Business Machines Corporation | Iteratively writing contents to memory locations using a statistical model |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8230276B2 (en) * | 2009-09-28 | 2012-07-24 | International Business Machines Corporation | Writing to memory using adaptive write techniques |
US8386739B2 (en) * | 2009-09-28 | 2013-02-26 | International Business Machines Corporation | Writing to memory using shared address buses |
EP2355105B1 (en) * | 2010-02-02 | 2013-01-09 | Nxp B.V. | Phase change memory programming method and phase change memory |
US8463985B2 (en) | 2010-03-31 | 2013-06-11 | International Business Machines Corporation | Constrained coding to reduce floating gate coupling in non-volatile memories |
JP5524115B2 (ja) * | 2011-03-22 | 2014-06-18 | 株式会社東芝 | 不揮発性半導体記憶装置 |
SI24265A (sl) * | 2012-11-30 | 2014-06-30 | Institut "Jožef Stefan" | Trajna bistabilna pomnilna naprava na osnovi ultrahitrega kaljenja |
US9837605B2 (en) | 2013-08-16 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell having resistance variable film and method of making the same |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
US9978810B2 (en) | 2015-11-04 | 2018-05-22 | Micron Technology, Inc. | Three-dimensional memory apparatuses and methods of use |
US10134470B2 (en) * | 2015-11-04 | 2018-11-20 | Micron Technology, Inc. | Apparatuses and methods including memory and operation of same |
US10446226B2 (en) | 2016-08-08 | 2019-10-15 | Micron Technology, Inc. | Apparatuses including multi-level memory cells and methods of operation of same |
US10157670B2 (en) * | 2016-10-28 | 2018-12-18 | Micron Technology, Inc. | Apparatuses including memory cells and methods of operation of same |
JP2018163971A (ja) * | 2017-03-24 | 2018-10-18 | 東芝メモリ株式会社 | 記憶装置 |
US10283704B2 (en) * | 2017-09-26 | 2019-05-07 | International Business Machines Corporation | Resistive memory device |
US10381075B2 (en) * | 2017-12-14 | 2019-08-13 | Micron Technology, Inc. | Techniques to access a self-selecting memory device |
US10546632B2 (en) | 2017-12-14 | 2020-01-28 | Micron Technology, Inc. | Multi-level self-selecting memory device |
US10522226B2 (en) * | 2018-05-01 | 2019-12-31 | Silicon Storage Technology, Inc. | Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2002326868A1 (en) * | 2002-09-11 | 2004-04-30 | Ovonyx, Inc. | Programming a phase-change material memory |
US20040257848A1 (en) * | 2003-06-18 | 2004-12-23 | Macronix International Co., Ltd. | Method for adjusting the threshold voltage of a memory cell |
US7236394B2 (en) * | 2003-06-18 | 2007-06-26 | Macronix International Co., Ltd. | Transistor-free random access memory |
KR100564602B1 (ko) * | 2003-12-30 | 2006-03-29 | 삼성전자주식회사 | 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로 |
US7465951B2 (en) * | 2005-01-19 | 2008-12-16 | Sandisk Corporation | Write-once nonvolatile phase change memory array |
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2007
- 2007-01-25 US US11/657,649 patent/US7626859B2/en active Active
- 2007-02-14 JP JP2007033804A patent/JP5111883B2/ja active Active
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US20070189065A1 (en) | 2007-08-16 |
US7626859B2 (en) | 2009-12-01 |
JP2007220281A (ja) | 2007-08-30 |
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