US11152064B2 - Memory device, memory cell and method for programming memory cell - Google Patents
Memory device, memory cell and method for programming memory cell Download PDFInfo
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- US11152064B2 US11152064B2 US16/530,517 US201916530517A US11152064B2 US 11152064 B2 US11152064 B2 US 11152064B2 US 201916530517 A US201916530517 A US 201916530517A US 11152064 B2 US11152064 B2 US 11152064B2
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- H01L27/2427—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0052—Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
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- H01L45/06—
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- H01L45/1233—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
Definitions
- Embodiments relate to a memory device, a memory cell and a method for programming a memory cell, and more particularly, to a memory device, a memory cell and a method for programming the memory cell, capable of utilizing a selective element as a storage element by inputting a write operation pulse having a falling edge period controlled to a selective element layer made of a specific composition of a material or extending a voltage margin of the storage element.
- a phase change random access memory also referred to as a phase change memory, is a non-volatile memory using a non-volatile phase change material instead of silicon.
- the PRAM has both advantages of non-volatility of a flash memory and high speed of a RAM.
- the PRAM is a memory semiconductor storing data using a phase change of a material, and when the phase changes from an amorphous state to a crystalline state, 1-bit data may be stored.
- the PRAM was based on the change from the amorphous state having high resistance to the crystalline state having low resistance when current flows to cells.
- a memory device includes a word line, a bit line between the word line, and a memory cell at an intersection point of the word line and the bit line.
- the memory cell may include: a first electrode connected to the word line; a second electrode connected to the bit line; and a first memory element layer between the first electrode and the second electrode.
- the first memory element layer may include one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.
- a method for programming a memory cell may include: applying a write operation pulse having a falling edge period extended to a memory cell including a first electrode, a second electrode, and a selective element layer between the first electrode and the second electrode, the selective element layer including a material altering a threshold voltage of the memory cell based on a falling edge period of the write operation pulse; and applying a read operation pulse to the memory cell.
- a memory cell may include: a first electrode; a second electrode; and a first memory element layer between the first electrode and the second electrode.
- the first memory element layer may include a material represented by one of Ge x Se y Te z (0.18 ⁇ x ⁇ 0.36, 0.4 ⁇ y ⁇ 0.65, and 0.02 ⁇ z ⁇ 0.2), Ge x Se y Te z As p (0.18 ⁇ x ⁇ 0.36, 0.4 ⁇ y ⁇ 0.65, 0.02 ⁇ z ⁇ 0.18, and 0.01 ⁇ p ⁇ 0.17), and Ge x Se y Te z As p Si q (0.14 ⁇ x ⁇ 0.32, 0.38 ⁇ y ⁇ 0.54, 0.02 ⁇ z ⁇ 0.18, 0.01 ⁇ p ⁇ 0.17, and 0.02 ⁇ q ⁇ 0.18).
- a memory cell may include: a first word line extending in a first direction; a second word line spaced apart from the first word line in a third direction, perpendicular to the first direction, and extending in the first direction; a bit line between the first word line and the second word line and extending in a second direction, perpendicular to the first direction and the third direction; a first memory cell between the first word line and the bit line; and a second memory cell between the second word line and the bit line.
- Each of the first and second memory cells may include a first electrode, a second electrode and at least one memory element layer between the first electrode and the second electrode.
- the memory element layer may include a chalcogenide material and be used as both a selective element layer and a storage element layer.
- FIG. 1 illustrates a graph of a threshold voltage characteristic of a comparative selective element
- FIG. 2 illustrates a graph of a threshold voltage characteristic of a memory cell including a comparative storage element
- FIG. 3 illustrates a graph of a threshold voltage characteristic of a memory cell according to an example embodiment
- FIG. 4 illustrates a graph of a threshold voltage characteristic of a memory cell according to another example embodiment
- FIG. 5 illustrates a perspective view of a structure of a memory cell according to an example embodiment
- FIGS. 6 and 7 illustrate perspective views of a structure of a memory cell according to example embodiments
- FIG. 8 illustrates a perspective view of a structure of a memory cell according to an example embodiment
- FIG. 9 illustrates a perspective view of a structure of a memory cell according to an example embodiment
- FIG. 10 illustrates a graph of a change of a threshold voltage of a memory cell having a SET state based on a falling edge period according to example embodiments
- FIG. 11 illustrates a graph of a change of a selective element layer based on a falling edge period and a change of a threshold voltage of a memory cell having a SET state according to example embodiments;
- FIG. 12 illustrates write operation pulses having various falling edge periods
- FIG. 13 illustrates a graph obtained experimentally of changes in a threshold voltage occurring when the write operation pulse having various falling edge periods illustrated in FIG. 12 is applied to a memory cell according to example embodiments;
- FIG. 14 illustrates a graph obtained experimentally of changes in a threshold voltage when the write operation pulse having various falling edge periods illustrated in FIG. 12 is applied to a comparative selective element
- FIG. 15 illustrates a graph obtained experimentally of a threshold voltage characteristic of a comparative memory cell obtained through experiments
- FIG. 16 illustrates a graph obtained experimentally of a threshold voltage characteristic of a memory cell according to an example embodiment
- FIGS. 17 and 18 illustrate graphs obtained experimentally of changes of a threshold voltage occurring when various falling edge periods are applied to the memory cell according to example embodiments when a read operation and a write operation are repeated;
- FIGS. 19 and 20 illustrate graphs obtained experimentally of changes of a threshold voltage occurring when a write operation pulse to which various falling edge periods are applied to a memory cell including a selective element layer having a low arsenic component according to example embodiments;
- FIG. 21 illustrates a flowchart of a method for programming a memory cell according to example embodiments.
- FIG. 1 illustrates a threshold voltage characteristic of a comparative selective element.
- FIG. 2 illustrates a threshold voltage characteristic of a comparative storage element.
- a memory consists of one selective element and one storage element.
- the selective element may be, for example, an ovonic threshold switch (OTS)
- the storage element may be, e.g., a GST.
- GST is a chalcogenide alloy of germanium (Ge), antimony (Sb), and tellurium (Te) (GeSbTe).
- the selective element may be an element selecting a cell and its electrical characteristic may be constant without being affected by a write operation pulse.
- a diode, a bipolar junction transistor (BJT), an N-channel metal oxide semiconductor (NMOS), and the like may be used as the selective element, and the threshold voltage Vth may not depend on a SET/RESET write operation pulse, but may have a constant value all the time as illustrated in FIG. 1 .
- a distribution curve 11 and a distribution curve 21 may almost be identical regardless of whether a set voltage or a reset voltage is applied thereto.
- Data stored may be distinguished according to changes of characteristics of the storage element.
- the PRAM may distinguish between 0 and 1 using the threshold voltage difference (or resistance difference) in a GST material.
- the PRAM has a low resistance and a low threshold voltage in a crystalline state, while having a high resistance and a high threshold voltage in an amorphous state.
- the threshold voltage Vth of a storage element depends on which voltage is applied thereto.
- FIG. 3 illustrates a threshold voltage characteristic of a memory cell according to an example embodiment.
- FIG. 4 illustrates a threshold voltage characteristic of a memory cell according to an example embodiment.
- a comparative selective element which was not used for the purpose of storage may be used as a storage device.
- the threshold voltage has a constant value regardless of the voltage applied thereto in the comparative selective element.
- the difference in the threshold voltage B of FIG. 3 between the distribution curve 21 and a distribution curve 15
- the SET/RESET may occur by lowering voltage distribution from the distribution curve 11 illustrated in FIG. 1 to the distribution curve 15 illustrated in FIG. 3 .
- embodiments provide a method of utilizing a multi-level PRAM by extending, e.g., increasing a margin of the comparative storage element.
- the difference in the threshold voltage between the SET/RESET may be further increased by lowering voltage distribution in the SET from the distribution curve 13 illustrated in FIGS. 2 and 4 to a distribution curve 17 illustrated in FIG. 4 .
- FIG. 2 unlike the characteristics of comparative storage elements having the difference in the threshold voltage between the SET/RESET of less than about 1.2, according to a memory cell proposed in example embodiments, the difference in the threshold voltage between the SET/RESET may be further increased by lowering voltage distribution in the SET from the distribution curve 13 illustrated in FIGS. 2 and 4 to a distribution curve 17 illustrated in FIG. 4 .
- FIG. 4 illustrates the difference in the threshold voltage between the SET/RESET of a memory cell to which a general storage memory cell is applied, i.e., A, is increased to C in example embodiments having the selective element having the above characteristics and a storage element.
- A the threshold voltage between the SET/RESET of a memory cell to which a general storage memory cell is applied
- FIG. 5 illustrates a structure of a memory cell according to an example embodiment.
- FIGS. 6 and 7 illustrate structures of a memory cell according to an example embodiment.
- FIG. 8 illustrates a structure of a memory cell according to an example embodiment.
- FIG. 9 illustrates a structure of a memory cell according to an example embodiment.
- a memory cell may include a first electrode 110 , a second electrode 120 , and a first memory element layer 150 .
- the first electrode 110 and the second electrode 120 may be connected to a word line 101 extending in a first direction DIR 1 and a bit line 103 extending in a second direction DIR 2 perpendicular to the first direction DIR 1 , respectively.
- the word line 101 and the bit line 103 may be spaced apart from each other in a third direction DIR 3 , perpendicular to the first direction DIR 1 and the second direction DIR 2 .
- a memory cell according to example embodiments may be formed at an intersection of the word line 101 and the bit line 103 , as illustrated in FIGS. 5 to 8 .
- the first memory element layer 150 may be formed between the first electrode 110 and the second electrode 120 .
- the first memory element layer 150 may include a material altering a threshold voltage of a memory cell based on a falling edge period of a write operation pulse.
- the material altering the threshold voltage of the memory cell based on the falling edge period of the write operation pulse may be one of Ge x Se y Te z (0.18 ⁇ x ⁇ 0.36, 0.4 ⁇ y ⁇ 0.65, and 0.02 ⁇ z ⁇ 0.2), Ge x Se y Te z As p (0.18 ⁇ x ⁇ 0.36, 0.4 ⁇ y ⁇ 0.56, 0.02 ⁇ z ⁇ 0.18, and 0.01 ⁇ p ⁇ 0.17), Ge x Se y Te z As p Si q (0.14 ⁇ x ⁇ 0.32, 0.38 ⁇ y ⁇ 0.54, 0.02 ⁇ z ⁇ 0.18, 0.01 ⁇ p ⁇ 0.17, and 0.02 ⁇ q ⁇ 0.18), and the like. All of these compositions either have no arsenic (As) or a lower ratio of arsenic (As) than other
- a structure of a memory cell according to example embodiments, as illustrated in FIGS. 6 to 8 may further include a third electrode 130 between the first electrode 110 and the second electrode 120 .
- a second memory element layer 140 may be formed between the first electrode 110 and the third electrode 130
- the first memory element layer 150 may be formed between the second electrode 120 and the third electrode 130 .
- the second memory element layer 140 may be formed between the second electrode 120 and the third electrode 130
- the first memory element layer 150 may be formed between the first electrode 110 and the third electrode 130 .
- a first selective element layer 151 may be formed between the first electrode 110 and the third electrode 130
- a second selective element layer 153 may be formed between the second electrode 120 and the third electrode 130
- Each of the first selective element layer and the second selective element layer may have a chalcogenide material, e.g., a Ge—Se—Te, Ge—Se—Te—As, Ge—Se—Te—As—Si.
- the types and/or the composition ratios of the materials included in the first selective element layer 151 and the second selective element layer 153 may be the same as or different from each other.
- each of a first memory cell 102 and a second memory cell 104 may include a first electrode 110 , a second electrode 120 , and a first memory element layer 150 .
- the first memory cell 102 may be disposed between a first word line 101 and a bit line 103 .
- the second memory cell 104 may be disposed between a bit line 103 and a second word line 105 .
- the first word line 101 and the second word line 105 may be extending in a first direction DIR 1 , and be space apart from each other in a third direction DIR 3 , perpendicular to the first direction DIR 1 and a second direction DIR 2 .
- the bit line 103 may be extending in a third direction DIR 2 , perpendicular to the first direction DIR 1 .
- Each of the first memory cell 102 and the second memory cell 104 may have another structure as illustrated in FIGS. 6 to 8 .
- each of the first memory cell 102 and the second memory cell 104 may further include a third electrode between the first electrode 110 and the second electrode 120 , and a second memory element layer.
- the first memory element layer may be disposed between the first electrode and the third electrode
- the second memory element layer may be disposed between the second electrode and the third electrode.
- the first memory element layer 150 and the second memory element layer may include a chalcogenide material altering a threshold voltage of each of the first and second memory cells 102 , 104 based on a falling edge period of a write operation pulse.
- the chalcogenide material may have no arsenic (As) or a lower ratio of arsenic (As) than other components of the material.
- Each of the first memory element layer 150 and the second memory element layer may be used as a selective element layer and/or a storage element layer.
- FIG. 10 is a graph of a change of a threshold voltage of a memory cell having a SET state based on a falling edge period according to example embodiments.
- FIG. 11 is a graph of a change of the selective element layer based on a falling edge period according to example embodiments and a change of a threshold voltage of a memory cell having a SET state.
- the selective element layers 150 , 151 , and 153 applied in example embodiments may have the threshold voltage of the memory cell, which is altered based on the falling edge period of the operation pulse as described above.
- a threshold voltage (Vth) value of the memory cell including the selective element layer may be lowered from about 4 V ( 211 ) to about 2.5 V ( 207 ). This is because, as illustrated in FIG. 11 , the size and the number of the crystalline structures formed in the selective element layer 150 , 151 , and 153 change based on the falling edge period of the operation pulse. Voltage distribution curves 221 , 223 , 225 and 227 illustrated in FIG.
- FIG. 12 illustrates a write operation pulse having various falling edge periods are applied thereto.
- FIG. 13 is a graph obtained experimentally that shows changes of a threshold voltage occurring when the write operation pulse having various edge periods illustrated in FIG. 12 are applied to a memory cell according to example embodiments.
- FIG. 14 is a graph obtained experimentally that shows changes of a threshold voltage occurring when the write operation pulse having various falling edge periods illustrated in FIG. 12 are applied to a comparative selective element.
- the change of the threshold voltage of the memory cell is illustrated in FIG. 13 , when the falling edge periods of the write operation pulse are set to 100 ns, 1 ⁇ s and 2 ⁇ s, respectively.
- the threshold voltage is lowered by about D compared to the case in which the falling edge period is 100 ns.
- a write operation pulse having different falling edge periods applied thereto is applied to a comparative selective element, there are negligible differences.
- the voltage distribution between SET/RESET may be further spaced than that of the comparative example, as may be seen by comparing FIG. 3 and FIG. 1 .
- the voltage distribution between the SET/RESET may be distinguished as illustrated in FIG. 3 , such that the selective element may be utilized as a memory even with a very simplified structure, as illustrated in FIG. 5 .
- the memory cell may be utilized as a multi-level cell capable of storing multi-bit data per cell. That is, according to a memory cell according to example embodiments, apart from a general flash memory storing 1-bit data per cell, a plurality of bits per cell may be stored by extending the voltage margin between the SET/RESET while having the same structure as a comparative cell.
- the voltage margin between the SET/RESET of the memory cell may be increased, e.g., to 2.3V, compared in to the comparative memory cell.
- FIG. 15 is a graph obtained experimentally illustrating a threshold voltage characteristic of a comparative memory cell.
- FIG. 16 is a graph obtained experimentally illustrating a threshold voltage characteristic of a memory cell according to an example embodiment.
- the difference (voltage margin, A) in the threshold voltage between the SET/RESET illustrated in FIG. 15 is increased, e.g., to C 1 or C 2 , as illustrated in FIG. 16 .
- Distribution curves 13 and 23 illustrated in FIG. 15 may correspond to voltage distribution curves between the SET/RESET illustrated in FIG. 2 , respectively.
- the voltage margins C 1 or C 2 , illustrated in FIG. 16 result from performing experiments under slightly different conditions, respectively, and show voltage margins of 2.04V and 2.09V, respectively, which are increased as compared with the voltage margin (A) illustrated in FIG. 15 .
- the memory cell proposed in example embodiments tends to decrease as the falling edge period of the write operation pulse becomes longer as described above. However, when a pulse having an increased falling edge period is applied again, the threshold voltage may be restored to its original magnitude. Therefore, before the next read operation is performed on the memory cell proposed in example embodiments, a write operation pulse having the short falling edge period may be applied again to the memory cell. For example, if a SET write operation pulse has a falling edge period of 1.5 ⁇ s, a RESET write operation pulse and a read operation pulse have a falling edge period of 10 ns, a difference between the SET and RESET in the threshold voltage of the selective element layer may be 2.3 V, after applying the SET write operation pulse to the memory cell.
- FIGS. 17 and 18 are graphs obtained experimentally showing changes of a threshold voltage occurring when various falling edge periods are applied to the memory cell according to example embodiments when the read operation and the write operation are repeated.
- FIGS. 17 and 18 illustrate results of applying a same read operation pulse and write operation pulses having different falling edge periods, e.g., 10 ns, 100 ns, 1 ⁇ s, and 10 ⁇ s, respectively.
- the resultant data of the read operation is commonly recorded in measurements 1 , 3 , 5 , 7 and 9 , respectively, and the resultant data of the write operation having different falling edge periods is recorded in measurements 2 , 4 , 6 and 8 , respectively.
- a threshold voltage value measured by setting the falling edge period of the write operation pulse at 10 ns is not significantly lowered, see voltage 31 , but a threshold voltage value decreases, see voltages 33 , 35 , and 37 , as the falling edge period increases, e.g., 100 ns, 1 ⁇ s, and 10 ⁇ s.
- Such a change in the threshold voltage may also be confirmed through graphs illustrated in the measurements 4 , 6 , and 8 in FIG. 18 .
- the selective element layers 150 , 151 , and 153 may include a material altering the threshold voltage of the memory cell based on the falling edge period of the write operation pulse.
- the material altering the threshold voltage of the memory cell based on the falling edge period of the write operation pulse has no arsenic (As) or a lower ratio of arsenic (As) than other components of the material.
- FIGS. 19 and 20 are graphs obtained experimentally that show changes of a threshold voltage occurring when the write operation pulse having various edge periods applied thereto is applied to the memory cell including a selective element layer having a low arsenic (As) component according to example embodiments.
- FIG. 19 illustrates an experimental data for a memory cell including a selective element layer made of Ge, As, Se, Te, Si components
- FIG. 20 illustrates an experimental data for a memory cell including a selective element layer made of Ge, As, Se, Te components.
- the threshold voltage decreases.
- the change of the threshold voltage is independent of an amplitude and a duration of the operation pulse.
- FIG. 21 is a flowchart of a method for programming a memory cell according to an example embodiment.
- a method for programming a memory cell may include applying a write operation pulse having a falling edge period extended (S 100 : a first operation) to a memory cell including a first electrode, a second electrode, and a selective element layer between the first electrode and the second electrode, and including a material altering a threshold voltage of a memory cell based on the falling edge period of the write operation pulse, and applying a read operation pulse (S 200 : a second operation) to a memory cell.
- a write operation pulse having a falling edge period extended S 100 : a first operation
- S 200 a second operation
- a memory cell having a simple structure including a layer including an OTS material may be used as a storage element or a read operation may be formed, after a read voltage margin of a memory cell having a structure illustrated in FIGS. 6 to 9 , is extended.
- a write operation pulse having a falling edge period extended (S 300 : a third operation) may be applied, and a preparation operation for the read operation may be performed again.
- the memory cell and the method for manufacturing the memory cell by inputting a write operation pulse having a falling edge period controlled to a selective element layer made of the specific composition of a material, and the selective element may be utilized as the storage element or may extend the voltage margin of the storage element.
- the selective element may be utilized as a storage element or the voltage margin of the storage element may be increased.
- One or more embodiments provide a memory device, a memory cell and a method for programming a memory cell capable of utilizing a selective element as a storage element by applying a write operation pulse having an increased falling edge period to a selective element layer made of a specific composition, the selective element may be utilized as a storage element or the voltage margin of the storage element may be increased.
Abstract
Description
Claims (19)
GexSeyTez [Formula 1]
GexSeyTezAsp [Formula 2]
GexSeyTezAspSiq [Formula 3]
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2018-0139645 | 2018-11-14 | ||
KR1020180139645A KR102614852B1 (en) | 2018-11-14 | 2018-11-14 | Memory device, memory cell and method for programing a memory cell |
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US20200152264A1 (en) | 2020-05-14 |
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