JP2002164428A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法Info
- Publication number
- JP2002164428A JP2002164428A JP2000362462A JP2000362462A JP2002164428A JP 2002164428 A JP2002164428 A JP 2002164428A JP 2000362462 A JP2000362462 A JP 2000362462A JP 2000362462 A JP2000362462 A JP 2000362462A JP 2002164428 A JP2002164428 A JP 2002164428A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating layer
- connection hole
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000362462A JP2002164428A (ja) | 2000-11-29 | 2000-11-29 | 半導体装置およびその製造方法 |
| TW090128124A TW541657B (en) | 2000-11-29 | 2001-11-13 | Semiconductor device and its fabrication method |
| US09/987,914 US6812127B2 (en) | 2000-11-29 | 2001-11-16 | Method of forming semiconductor device including silicon oxide with fluorine, embedded wiring layer, via holes, and wiring grooves |
| KR1020010074455A KR100830666B1 (ko) | 2000-11-29 | 2001-11-28 | 반도체장치 및 그 제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000362462A JP2002164428A (ja) | 2000-11-29 | 2000-11-29 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002164428A true JP2002164428A (ja) | 2002-06-07 |
| JP2002164428A5 JP2002164428A5 (enExample) | 2005-02-03 |
Family
ID=18833731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000362462A Pending JP2002164428A (ja) | 2000-11-29 | 2000-11-29 | 半導体装置およびその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6812127B2 (enExample) |
| JP (1) | JP2002164428A (enExample) |
| KR (1) | KR100830666B1 (enExample) |
| TW (1) | TW541657B (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004105123A1 (ja) * | 2003-05-21 | 2004-12-02 | Fujitsu Limited | 半導体装置 |
| JP2007129223A (ja) * | 2005-11-02 | 2007-05-24 | Internatl Business Mach Corp <Ibm> | 半導体構造およびその製作方法(チャネルの応力向上のための低ヤング率スペーサ) |
| US7323781B2 (en) | 2003-03-25 | 2008-01-29 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
| US8012871B2 (en) | 2002-10-17 | 2011-09-06 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| JPWO2010125682A1 (ja) * | 2009-04-30 | 2012-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (45)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
| TW544855B (en) * | 2001-06-25 | 2003-08-01 | Nec Electronics Corp | Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer |
| US7474002B2 (en) * | 2001-10-30 | 2009-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having dielectric film having aperture portion |
| JP2003257970A (ja) * | 2002-02-27 | 2003-09-12 | Nec Electronics Corp | 半導体装置及びその配線構造 |
| TWI300971B (en) * | 2002-04-12 | 2008-09-11 | Hitachi Ltd | Semiconductor device |
| JP3989763B2 (ja) * | 2002-04-15 | 2007-10-10 | 株式会社半導体エネルギー研究所 | 半導体表示装置 |
| TWI288443B (en) | 2002-05-17 | 2007-10-11 | Semiconductor Energy Lab | SiN film, semiconductor device, and the manufacturing method thereof |
| JP2004014841A (ja) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP2004031439A (ja) * | 2002-06-21 | 2004-01-29 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
| US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
| JP2004165559A (ja) * | 2002-11-15 | 2004-06-10 | Toshiba Corp | 半導体装置 |
| JP4489345B2 (ja) * | 2002-12-13 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| NL1023275C2 (nl) * | 2003-04-25 | 2004-10-27 | Cavendish Kinetics Ltd | Werkwijze voor het vervaardigen van een micro-mechanisch element. |
| TWI286814B (en) * | 2003-04-28 | 2007-09-11 | Fujitsu Ltd | Fabrication process of a semiconductor device |
| US7096450B2 (en) * | 2003-06-28 | 2006-08-22 | International Business Machines Corporation | Enhancement of performance of a conductive wire in a multilayered substrate |
| TWI285938B (en) * | 2003-08-28 | 2007-08-21 | Fujitsu Ltd | Semiconductor device |
| KR100605505B1 (ko) * | 2004-06-04 | 2006-07-31 | 삼성전자주식회사 | 버퍼막 패턴을 갖는 반도체 장치들 및 그들의 형성방법들 |
| JP2006024811A (ja) * | 2004-07-09 | 2006-01-26 | Sony Corp | 半導体装置の製造方法 |
| JP4185478B2 (ja) * | 2004-07-23 | 2008-11-26 | 長野計器株式会社 | 歪検出器およびその製造方法 |
| JP2006140404A (ja) * | 2004-11-15 | 2006-06-01 | Renesas Technology Corp | 半導体装置 |
| JP2006210508A (ja) * | 2005-01-26 | 2006-08-10 | Sony Corp | 半導体装置およびその製造方法 |
| US7414275B2 (en) * | 2005-06-24 | 2008-08-19 | International Business Machines Corporation | Multi-level interconnections for an integrated circuit chip |
| JP2007019188A (ja) * | 2005-07-06 | 2007-01-25 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
| JP2007123509A (ja) * | 2005-10-27 | 2007-05-17 | Seiko Epson Corp | 半導体装置およびその製造方法 |
| US7670927B2 (en) * | 2006-05-16 | 2010-03-02 | International Business Machines Corporation | Double-sided integrated circuit chips |
| US8013342B2 (en) * | 2007-11-14 | 2011-09-06 | International Business Machines Corporation | Double-sided integrated circuit chips |
| US7602027B2 (en) * | 2006-12-29 | 2009-10-13 | Semiconductor Components Industries, L.L.C. | Semiconductor component and method of manufacture |
| DE102007037858B4 (de) * | 2007-08-10 | 2012-04-19 | Infineon Technologies Ag | Halbleiterbauelement mit verbessertem dynamischen Verhalten |
| US20090079072A1 (en) * | 2007-09-21 | 2009-03-26 | Casio Computer Co., Ltd. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
| US8587124B2 (en) * | 2007-09-21 | 2013-11-19 | Teramikros, Inc. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
| TWI419268B (zh) * | 2007-09-21 | 2013-12-11 | 兆裝微股份有限公司 | 半導體裝置及其製造方法 |
| JP4666028B2 (ja) * | 2008-03-31 | 2011-04-06 | カシオ計算機株式会社 | 半導体装置 |
| US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
| US8354339B2 (en) * | 2010-07-20 | 2013-01-15 | International Business Machines Corporation | Methods to form self-aligned permanent on-chip interconnect structures |
| US8642460B2 (en) * | 2011-06-08 | 2014-02-04 | International Business Machines Corporation | Semiconductor switching device and method of making the same |
| CN102332425A (zh) * | 2011-09-23 | 2012-01-25 | 复旦大学 | 一种提升铜互连技术中抗电迁移特性的方法 |
| US8640072B1 (en) | 2012-07-31 | 2014-01-28 | Freescale Semiconductor, Inc. | Method for forming an electrical connection between metal layers |
| US9032615B2 (en) | 2012-07-31 | 2015-05-19 | Freescale Semiconductor, Inc. | Method for forming an electrical connection between metal layers |
| TWI613709B (zh) * | 2013-02-20 | 2018-02-01 | 財團法人工業技術研究院 | 半導體元件結構及其製造方法與應用其之畫素結構 |
| US10541204B2 (en) * | 2015-10-20 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and method of forming the same |
| TWI590350B (zh) * | 2016-06-30 | 2017-07-01 | 欣興電子股份有限公司 | 線路重分佈結構的製造方法與線路重分佈結構單元 |
| US9735015B1 (en) * | 2016-12-05 | 2017-08-15 | United Microelectronics Corporation | Fabricating method of semiconductor structure |
| KR102307127B1 (ko) * | 2017-06-14 | 2021-10-05 | 삼성전자주식회사 | 반도체 소자 |
| US20200312768A1 (en) * | 2019-03-27 | 2020-10-01 | Intel Corporation | Controlled organic layers to enhance adhesion to organic dielectrics and process for forming such |
| KR102859459B1 (ko) | 2020-09-02 | 2025-09-12 | 삼성전자주식회사 | 배선 구조체 및 이를 포함하는 반도체 패키지 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3399154B2 (ja) | 1995-05-22 | 2003-04-21 | ソニー株式会社 | 積層絶縁膜のプラズマエッチング方法 |
| JPH09306988A (ja) | 1996-03-13 | 1997-11-28 | Sony Corp | 多層配線の形成方法 |
| US6048789A (en) * | 1997-02-27 | 2000-04-11 | Vlsi Technology, Inc. | IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids |
| US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
| US6171957B1 (en) | 1997-07-16 | 2001-01-09 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of semiconductor device having high pressure reflow process |
| JPH11111845A (ja) * | 1997-10-03 | 1999-04-23 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6181012B1 (en) | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
| US6355571B1 (en) * | 1998-11-17 | 2002-03-12 | Applied Materials, Inc. | Method and apparatus for reducing copper oxidation and contamination in a semiconductor device |
| JP2000174019A (ja) * | 1998-12-01 | 2000-06-23 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| US6177364B1 (en) * | 1998-12-02 | 2001-01-23 | Advanced Micro Devices, Inc. | Integration of low-K SiOF for damascene structure |
| US6242349B1 (en) | 1998-12-09 | 2001-06-05 | Advanced Micro Devices, Inc. | Method of forming copper/copper alloy interconnection with reduced electromigration |
| JP3974284B2 (ja) | 1999-03-18 | 2007-09-12 | 株式会社東芝 | 半導体装置の製造方法 |
| JP4460669B2 (ja) * | 1999-03-19 | 2010-05-12 | 株式会社東芝 | 半導体装置 |
| US6211063B1 (en) * | 1999-05-25 | 2001-04-03 | Taiwan Semiconductor Manufacturing Company | Method to fabricate self-aligned dual damascene structures |
| JP4108228B2 (ja) * | 1999-07-15 | 2008-06-25 | 富士通株式会社 | 半導体装置の製造方法 |
| US6521532B1 (en) | 1999-07-22 | 2003-02-18 | James A. Cunningham | Method for making integrated circuit including interconnects with enhanced electromigration resistance |
| US6136680A (en) | 2000-01-21 | 2000-10-24 | Taiwan Semiconductor Manufacturing Company | Methods to improve copper-fluorinated silica glass interconnects |
| US6284644B1 (en) * | 2000-10-10 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | IMD scheme by post-plasma treatment of FSG and TEOS oxide capping layer |
-
2000
- 2000-11-29 JP JP2000362462A patent/JP2002164428A/ja active Pending
-
2001
- 2001-11-13 TW TW090128124A patent/TW541657B/zh not_active IP Right Cessation
- 2001-11-16 US US09/987,914 patent/US6812127B2/en not_active Expired - Fee Related
- 2001-11-28 KR KR1020010074455A patent/KR100830666B1/ko not_active Expired - Fee Related
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8012871B2 (en) | 2002-10-17 | 2011-09-06 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US8431480B2 (en) | 2003-03-25 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9064870B2 (en) | 2003-03-25 | 2015-06-23 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US7323781B2 (en) | 2003-03-25 | 2008-01-29 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
| US7777343B2 (en) | 2003-03-25 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
| US10304726B2 (en) | 2003-03-25 | 2019-05-28 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US8053893B2 (en) | 2003-03-25 | 2011-11-08 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US10121693B2 (en) | 2003-03-25 | 2018-11-06 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US8810034B2 (en) | 2003-03-25 | 2014-08-19 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US8617981B2 (en) | 2003-03-25 | 2013-12-31 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9818639B2 (en) | 2003-03-25 | 2017-11-14 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9659867B2 (en) | 2003-03-25 | 2017-05-23 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| US9490213B2 (en) | 2003-03-25 | 2016-11-08 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
| WO2004105123A1 (ja) * | 2003-05-21 | 2004-12-02 | Fujitsu Limited | 半導体装置 |
| US7170177B2 (en) | 2003-05-21 | 2007-01-30 | Fujitsu Limited | Semiconductor apparatus |
| JP2007129223A (ja) * | 2005-11-02 | 2007-05-24 | Internatl Business Mach Corp <Ibm> | 半導体構造およびその製作方法(チャネルの応力向上のための低ヤング率スペーサ) |
| JPWO2010125682A1 (ja) * | 2009-04-30 | 2012-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US6812127B2 (en) | 2004-11-02 |
| KR20020042458A (ko) | 2002-06-05 |
| US20020100984A1 (en) | 2002-08-01 |
| KR100830666B1 (ko) | 2008-05-20 |
| TW541657B (en) | 2003-07-11 |
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