CN102332425A - 一种提升铜互连技术中抗电迁移特性的方法 - Google Patents

一种提升铜互连技术中抗电迁移特性的方法 Download PDF

Info

Publication number
CN102332425A
CN102332425A CN201110285221A CN201110285221A CN102332425A CN 102332425 A CN102332425 A CN 102332425A CN 201110285221 A CN201110285221 A CN 201110285221A CN 201110285221 A CN201110285221 A CN 201110285221A CN 102332425 A CN102332425 A CN 102332425A
Authority
CN
China
Prior art keywords
copper
interconnecting line
copper interconnecting
electromigration resistance
cover layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201110285221A
Other languages
English (en)
Inventor
孙清清
陈琳
杨雯
王鹏飞
张卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to CN201110285221A priority Critical patent/CN102332425A/zh
Publication of CN102332425A publication Critical patent/CN102332425A/zh
Priority to US13/528,474 priority patent/US9153500B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

本发明属于半导体集成电路技术领域，具体涉及一种用于32纳米及以下工艺中提升铜互连线的抗电迁移特性的方法。在铜互连线上采用自对准工艺制备CuSi3、CuGe、CuSiN等覆盖层，加上新型阻挡层材料的使用，可以大大提高铜互连线的抗电迁移特性并且保持铜互连线的高导电性能，为32纳米及以下工艺节点中提供了理想的互连结构工艺解决方案。

Description

一种提升铜互连技术中抗电迁移特性的方法
技术领域
本发明属于半导体集成电路技术领域，具体涉及一种提升铜互连技术中抗电迁移特性的方法。
背景技术
随着半导体器件特征尺寸的不断缩小，芯片面积持续增大，人们面临着如何克服由于连线长度的急速增长而带来的RC(R指电阻，C指电容)延迟显著增加的问题，这已经成为半导体工业进一步发展的关键制约因素。为了减小互连造成的RC延迟 , 现已采用了多种措施。
与传统的铝相比，铜具有以下优点：第一，铜的电阻率更小 (Cu: 1.7μΩ/cm, Al: 3μΩ/cm)。第二，铜互连线的寄生电容比铝互连线小。由于铜的电阻率比铝低，导电性好，在承受相同电流时，铜互连线横截面积比铝互连线小，因而相邻导线间的寄生电容小，信号串扰也小。铜互连线的时间参数RC比铝互连小，信号在铜互连线上传输的速度也比铝互连快，这对高速IC是很有利的。第三，铜互连线的电阻小，使得铜互连线上功耗比铝互连小。第四，铜的抗电迁移率比铝好（Cu<107A/cm2，Al<106A/cm2),不会因为电迁移产生连线空洞，从而提高了器件可靠性。因此，采用金属Cu作为互连金属能够使器件具有更高的可靠性。目前，最佳的集成电路互连线系统是Cu/low-k （低介电常数）介质互连系统,与传统的互连线系统相比,Cu/low-k介质互连系统具有金属互连线层数目少、芯片速度高、功耗低、制造成本低、高抗电迁移性能等优势。
但是，随着半导体器件特征尺寸的持续缩小，Cu/low-k介质互连系统中对铜的抗迁移特性提出了越来越高的要求。在铜互连线上制备一层硅化物覆盖层是一种有效解决抗电迁移率问题的手段，但是在高温条件下，硅在铜中具有的极高的扩散系数会导致互连线电阻的大幅增加，这使得选择合适的覆盖层以及开发适当的互连工艺成为工业界目前急需解决的问题。
发明内容
本发明的目的在于提出一种合适的铜互连线的覆盖层的制造方法，以便在不增加互连线电阻的同时提升铜互连线的抗电迁移特性。
本发明提出的提升铜互连线的抗电迁移特性的方法，具体步骤包括：
提供一个半导体衬底；
利用通常的标准CMOS工艺完成前道MOS器件的制备；
形成第一层绝缘介质；
光刻、刻蚀定义出互连位置；
形成扩散阻挡层；
形成铜互连线；
在铜互连线上制备覆盖层；
刻蚀部分用于后续互连的所述铜互连线上的覆盖层；
利用双镶嵌工艺形成后续铜互连线结构；
在后续形成的铜互连线上制备覆盖层。
进一步地，所述的第一层绝缘介质为氧化硅、氮化硅或者为氟硅玻璃等低k介质材料。
更进一步地，所述的在铜互连线上制备覆盖层的具体步骤为：
在铜互连线上形成第一材料层；
高温退火形成含铜化合物覆盖层；
刻蚀掉剩余的第一材料层。
其中，所述的第一材料为硅或者锗。
进一步地，为了提高性能，在铜互连线上形成所述的含铜化合物覆盖层之后，通过氮化工艺形成新的含氮和铜的化合物覆盖层。
附图说明
图1至图8为利用本发明所提供的提升铜互连线的抗电迁移特性的方法来制备COMS器件的工艺流程图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细的说明，在图中，为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不能完全准确的反映出器件的实际尺寸，但是它们还是完整的反映了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。参考图是本发明的理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。例如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中，均以矩形表示，图中的表示是示意性的，但这不应该被认为是限制本发明的范围。同时在下面的描述中，所使用的术语衬底可以理解为包括正在工艺加工中的半导体衬底，可能包括在其上所制备的其它薄膜层。
本发明所提出的提升铜互连线的抗电迁移特性的方法可以适用于不同MOS器件的后道互连结构中，以下所叙述的是在22纳米工艺中制备CMOS器件的铜互连线的CuSiN覆盖层为实施例的工艺流程。
首先，提供一个半导体衬底201，然后采用标准CMOS工艺，完成前道CMOS器件的制备，如图1所示，其具体的工艺包括有：1.在衬底201内形成浅槽隔离结构202，这种工艺是业界所述熟知的。2. 采用扩散工艺或者离子注入工艺在衬底201内形成n阱201a和p阱201b。3采用氧化工艺、薄膜淀积工艺以及光刻工艺和刻蚀工艺，在衬底201上形成PMOS器件的栅氧化层203a、栅电极204a、栅极侧墙205a以及NMOS器件的栅氧化层203b、栅电极204b、栅极侧墙205b。3.采用扩散工艺或者离子注入工艺，形成PMOS器件的源区206a、漏区206b以及NMOS器件的源区207a、漏区207b（金属与半导体的接触），从而完成CMOS器件的前道制造工艺。
接下来，利用化学气相沉积（CVD）方法淀积SiOC 低k介质材料来形成层间隔离层208，然后光刻、刻蚀定义出互连通孔位置，并利用反应离子溅射一层TiN，用来作为铜的扩散阻挡层，然后利用原子层淀积（ALD）技术在TiN上生长Ru层形成Ru/TiN结构209。接着采用电镀方法形成铜连线210，并用化学机械抛光（CMP）技术平整化wafer表面,如图2所示。
接下来，利用SiH4作为CVD前躯体在wafer上淀积形成硅层211，如图3所示。接着，利用退火工艺形成硅化铜，然后腐蚀掉剩余的硅层，再经过NH3的plasma处理后在铜互连线210的表面形成CuSiN化合物覆盖层212，如图4所示。
接下来，淀积一层氮化硅刻蚀阻挡层213，并再次淀积SiOC层间隔离层214，然后光刻、刻蚀定义出第二层互连位置，然后选择性腐蚀掉部分CuSiN覆盖层212以减少后续铜互连线的阻值，如图5所示。
接下来，再次淀积形成Ru/TiN扩散阻挡层215，并电镀铜互连线216，之后采用CMP技术抛光，如图6所示。
接下来，在第二层铜互连线216上形成CuSiN化合物覆盖层217，如图7所示。
最后，利用双镶嵌工艺形成后续铜互连结构，并采用之前的形成CuSiN的相同工艺形成铜互连线的CuSiN覆盖层222，如图8所示，其中，所示218为氮化硅刻蚀阻挡层，所示219为氟硅玻璃低k介质材料，所示220为Ru/TiN结构的扩散阻挡层，所示221为铜互连线。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。

Claims (5)

1.一种提升铜互连线的抗电迁移特性的方法，其特征在于具体步骤包括：
提供一个半导体衬底；
利用通常CMOS工艺完成前道MOS器件的制备；
形成第一层绝缘介质；
光刻、刻蚀定义出互连位置；
形成扩散阻挡层；
形成铜互连线；
在铜互连线上制备覆盖层；
刻蚀部分用于后续互连的所述铜互连线上的覆盖层；
利用双镶嵌工艺形成后续铜互连线结构；
在后续形成的铜互连线上制备覆盖层。
2.根据权利要求1所述的提升铜互连线的抗电迁移特性的方法，其特征在于，所述的第一层绝缘介质为氧化硅、氮化硅或者氟硅玻璃。
3.根据权利要求1所述的提升铜互连线的抗电迁移特性的方法，其特征在于，所述的在铜互连线上制备覆盖层的具体步骤为：
在铜互连线上形成第一材料层；
高温退火形成含铜化合物覆盖层；
刻蚀掉剩余的第一材料层。
4.根据权利要求3所述的提升铜互连线的抗电迁移特性的方法，其特征在于，所述的第一材料为硅或者锗。
5.根据权利要求3所述的提升铜互连线的抗电迁移特性的方法，其特征在于，在铜互连线上形成所述的含铜化合物覆盖层之后，通过氮化工艺形成新的含氮和铜的化合物覆盖层。
CN201110285221A 2011-09-23 2011-09-23 一种提升铜互连技术中抗电迁移特性的方法 Pending CN102332425A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201110285221A CN102332425A (zh) 2011-09-23 2011-09-23 一种提升铜互连技术中抗电迁移特性的方法
US13/528,474 US9153500B2 (en) 2011-09-23 2012-06-20 Method for improving the electromigration resistance in the copper interconnection process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110285221A CN102332425A (zh) 2011-09-23 2011-09-23 一种提升铜互连技术中抗电迁移特性的方法

Publications (1)

Publication Number Publication Date
CN102332425A true CN102332425A (zh) 2012-01-25

Family

ID=45484150

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110285221A Pending CN102332425A (zh) 2011-09-23 2011-09-23 一种提升铜互连技术中抗电迁移特性的方法

Country Status (2)

Country Link
US (1) US9153500B2 (zh)
CN (1) CN102332425A (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593098A (zh) * 2012-02-27 2012-07-18 北京大学 一种集成电路金属互连结构及其制备方法
CN104835777A (zh) * 2014-02-08 2015-08-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
WO2016058174A1 (en) * 2014-10-17 2016-04-21 Acm Research (Shanghai) Inc. Barrier layer removal method and semiconductor structure forming method
CN106505031A (zh) * 2015-09-07 2017-03-15 中芯国际集成电路制造(上海)有限公司 一种铜互连结构的制作方法、铜互连结构及电子装置
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法
CN109003939A (zh) * 2014-10-13 2018-12-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制作方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US10685873B2 (en) 2016-06-29 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Etch stop layer for semiconductor devices
US10109524B2 (en) * 2017-01-24 2018-10-23 Globalfoundries Inc. Recessing of liner and conductor for via formation
US10181421B1 (en) * 2017-07-12 2019-01-15 Globalfoundries Inc. Liner recess for fully aligned via

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100984A1 (en) * 2000-11-29 2002-08-01 Hitachi, Ltd. Semiconductor device and its fabrication method
KR20030002021A (ko) * 2001-06-30 2003-01-08 주식회사 하이닉스반도체 캐패시터의 제조 방법
EP1021827B1 (en) * 1997-08-19 2007-04-25 Applied Materials, Inc. Dual damascene metallization
US20100308463A1 (en) * 2009-06-03 2010-12-09 Jengyi Yu Interfacial capping layers for interconnects

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420069A (en) * 1992-12-31 1995-05-30 International Business Machines Corporation Method of making corrosion resistant, low resistivity copper for interconnect metal lines
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
US20040207093A1 (en) * 2003-04-17 2004-10-21 Sey-Shing Sun Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects
US20070194450A1 (en) * 2006-02-21 2007-08-23 Tyberg Christy S BEOL compatible FET structure
US7718548B2 (en) * 2006-12-06 2010-05-18 Applied Materials, Inc. Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface
US7816789B2 (en) * 2006-12-06 2010-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium-containing dielectric barrier for low-k process
JP5380901B2 (ja) * 2008-05-12 2014-01-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1021827B1 (en) * 1997-08-19 2007-04-25 Applied Materials, Inc. Dual damascene metallization
US20020100984A1 (en) * 2000-11-29 2002-08-01 Hitachi, Ltd. Semiconductor device and its fabrication method
KR20030002021A (ko) * 2001-06-30 2003-01-08 주식회사 하이닉스반도체 캐패시터의 제조 방법
US20100308463A1 (en) * 2009-06-03 2010-12-09 Jengyi Yu Interfacial capping layers for interconnects

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593098A (zh) * 2012-02-27 2012-07-18 北京大学 一种集成电路金属互连结构及其制备方法
CN104835777A (zh) * 2014-02-08 2015-08-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
CN104835777B (zh) * 2014-02-08 2017-11-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
CN109003939A (zh) * 2014-10-13 2018-12-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制作方法
WO2016058174A1 (en) * 2014-10-17 2016-04-21 Acm Research (Shanghai) Inc. Barrier layer removal method and semiconductor structure forming method
CN107078065A (zh) * 2014-10-17 2017-08-18 盛美半导体设备（上海）有限公司 阻挡层的去除方法以及半导体结构的形成方法
CN106505031A (zh) * 2015-09-07 2017-03-15 中芯国际集成电路制造(上海)有限公司 一种铜互连结构的制作方法、铜互连结构及电子装置
CN106505031B (zh) * 2015-09-07 2019-12-31 中芯国际集成电路制造(上海)有限公司 一种铜互连结构的制作方法、铜互连结构及电子装置
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法

Also Published As

Publication number Publication date
US9153500B2 (en) 2015-10-06
US20130078798A1 (en) 2013-03-28

Similar Documents

Publication Publication Date Title
CN102332425A (zh) 一种提升铜互连技术中抗电迁移特性的方法
US7119005B2 (en) Semiconductor local interconnect and contact
CN101814475B (zh) 用于衬底通孔的阻挡结构和方法
TWI497591B (zh) 製造具有自動對準介電帽之互連結構的結構及方法
CN102738068A (zh) 半导体器件及其制造方法
US11349004B2 (en) Backside vias in semiconductor device
US20080157380A1 (en) Method for forming metal interconnection of semiconductor device
JP2003152077A (ja) 半導体装置および半導体装置の製造方法
US11532714B2 (en) Semiconductor device and method of forming thereof
CN102364670B (zh) 金属铜大马士革互联结构的制造方法
US9224691B2 (en) Semiconductor device contact structures
CN108183087B (zh) 用于形成应力降低装置的方法
US10224242B1 (en) Low-resistivity metallic interconnect structures
US8304834B2 (en) Semiconductor local interconnect and contact
US20080048332A1 (en) Method for forming intermetal dielectric in semiconductor device
KR101496550B1 (ko) 상호연결 구조물을 형성하는 방법
CN103050433A (zh) 半导体的接触孔结构及其制作方法
CN102437100A (zh) 一种使用双大马士革工艺同时形成铜接触孔和第一层金属的方法
CN103187298B (zh) 金属栅极场效应晶体管及其制作方法
CN102324403B (zh) 超低介电常数薄膜铜互连的制作方法
US20040203228A1 (en) Method of forming a tungsten plug
TWI782473B (zh) 半導體元件及其製造方法
CN102420212A (zh) 超低介电常数薄膜铜互连结构及其制作方法
US7638425B2 (en) Metal line of semiconductor device having a diffusion barrier including CRxBy and method for forming the same
TWI746851B (zh) 金屬內連線結構及其製作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120125