KR100830666B1 - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR100830666B1
KR100830666B1 KR1020010074455A KR20010074455A KR100830666B1 KR 100830666 B1 KR100830666 B1 KR 100830666B1 KR 1020010074455 A KR1020010074455 A KR 1020010074455A KR 20010074455 A KR20010074455 A KR 20010074455A KR 100830666 B1 KR100830666 B1 KR 100830666B1
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South Korea
Prior art keywords
wiring
insulating layer
connection hole
film
insulating film
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Expired - Fee Related
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KR1020010074455A
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English (en)
Korean (ko)
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KR20020042458A (ko
Inventor
오오시마타카유키
미야자키히로시
아오키히데오
오오모리카즈토시
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가부시키가이샤 히타치세이사쿠쇼
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835Combinations of two or more different dielectric layers having a low dielectric constant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036Dual damascene with different via-level and trench-level dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
KR1020010074455A 2000-11-29 2001-11-28 반도체장치 및 그 제조방법 Expired - Fee Related KR100830666B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2000-00362462 2000-11-29
JP2000362462A JP2002164428A (ja) 2000-11-29 2000-11-29 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
KR20020042458A KR20020042458A (ko) 2002-06-05
KR100830666B1 true KR100830666B1 (ko) 2008-05-20

Family

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Family Applications (1)

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KR1020010074455A Expired - Fee Related KR100830666B1 (ko) 2000-11-29 2001-11-28 반도체장치 및 그 제조방법

Country Status (4)

Country Link
US (1) US6812127B2 (enExample)
JP (1) JP2002164428A (enExample)
KR (1) KR100830666B1 (enExample)
TW (1) TW541657B (enExample)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
TW544855B (en) * 2001-06-25 2003-08-01 Nec Electronics Corp Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer
US7474002B2 (en) * 2001-10-30 2009-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having dielectric film having aperture portion
JP2003257970A (ja) * 2002-02-27 2003-09-12 Nec Electronics Corp 半導体装置及びその配線構造
TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
JP3989763B2 (ja) * 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
TWI288443B (en) 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
JP2004014841A (ja) * 2002-06-07 2004-01-15 Fujitsu Ltd 半導体装置及びその製造方法
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
CN100352036C (zh) 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
US6917108B2 (en) * 2002-11-14 2005-07-12 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
JP2004165559A (ja) * 2002-11-15 2004-06-10 Toshiba Corp 半導体装置
JP4489345B2 (ja) * 2002-12-13 2010-06-23 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4454242B2 (ja) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
NL1023275C2 (nl) * 2003-04-25 2004-10-27 Cavendish Kinetics Ltd Werkwijze voor het vervaardigen van een micro-mechanisch element.
TWI286814B (en) * 2003-04-28 2007-09-11 Fujitsu Ltd Fabrication process of a semiconductor device
JP4868742B2 (ja) 2003-05-21 2012-02-01 富士通株式会社 半導体装置
US7096450B2 (en) * 2003-06-28 2006-08-22 International Business Machines Corporation Enhancement of performance of a conductive wire in a multilayered substrate
TWI285938B (en) * 2003-08-28 2007-08-21 Fujitsu Ltd Semiconductor device
KR100605505B1 (ko) * 2004-06-04 2006-07-31 삼성전자주식회사 버퍼막 패턴을 갖는 반도체 장치들 및 그들의 형성방법들
JP2006024811A (ja) * 2004-07-09 2006-01-26 Sony Corp 半導体装置の製造方法
JP4185478B2 (ja) * 2004-07-23 2008-11-26 長野計器株式会社 歪検出器およびその製造方法
JP2006140404A (ja) * 2004-11-15 2006-06-01 Renesas Technology Corp 半導体装置
JP2006210508A (ja) * 2005-01-26 2006-08-10 Sony Corp 半導体装置およびその製造方法
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
JP2007019188A (ja) * 2005-07-06 2007-01-25 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP2007123509A (ja) * 2005-10-27 2007-05-17 Seiko Epson Corp 半導体装置およびその製造方法
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US7670927B2 (en) * 2006-05-16 2010-03-02 International Business Machines Corporation Double-sided integrated circuit chips
US8013342B2 (en) * 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US7602027B2 (en) * 2006-12-29 2009-10-13 Semiconductor Components Industries, L.L.C. Semiconductor component and method of manufacture
DE102007037858B4 (de) * 2007-08-10 2012-04-19 Infineon Technologies Ag Halbleiterbauelement mit verbessertem dynamischen Verhalten
US20090079072A1 (en) * 2007-09-21 2009-03-26 Casio Computer Co., Ltd. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US8587124B2 (en) * 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
TWI419268B (zh) * 2007-09-21 2013-12-11 兆裝微股份有限公司 半導體裝置及其製造方法
JP4666028B2 (ja) * 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
WO2010125682A1 (ja) * 2009-04-30 2010-11-04 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8304863B2 (en) 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8354339B2 (en) * 2010-07-20 2013-01-15 International Business Machines Corporation Methods to form self-aligned permanent on-chip interconnect structures
US8642460B2 (en) * 2011-06-08 2014-02-04 International Business Machines Corporation Semiconductor switching device and method of making the same
CN102332425A (zh) * 2011-09-23 2012-01-25 复旦大学 一种提升铜互连技术中抗电迁移特性的方法
US8640072B1 (en) 2012-07-31 2014-01-28 Freescale Semiconductor, Inc. Method for forming an electrical connection between metal layers
US9032615B2 (en) 2012-07-31 2015-05-19 Freescale Semiconductor, Inc. Method for forming an electrical connection between metal layers
TWI613709B (zh) * 2013-02-20 2018-02-01 財團法人工業技術研究院 半導體元件結構及其製造方法與應用其之畫素結構
US10541204B2 (en) * 2015-10-20 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and method of forming the same
TWI590350B (zh) * 2016-06-30 2017-07-01 欣興電子股份有限公司 線路重分佈結構的製造方法與線路重分佈結構單元
US9735015B1 (en) * 2016-12-05 2017-08-15 United Microelectronics Corporation Fabricating method of semiconductor structure
KR102307127B1 (ko) * 2017-06-14 2021-10-05 삼성전자주식회사 반도체 소자
US20200312768A1 (en) * 2019-03-27 2020-10-01 Intel Corporation Controlled organic layers to enhance adhesion to organic dielectrics and process for forming such
KR102859459B1 (ko) 2020-09-02 2025-09-12 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174019A (ja) * 1998-12-01 2000-06-23 Fujitsu Ltd 半導体装置及びその製造方法
JP2000269337A (ja) * 1999-03-19 2000-09-29 Toshiba Corp 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3399154B2 (ja) 1995-05-22 2003-04-21 ソニー株式会社 積層絶縁膜のプラズマエッチング方法
JPH09306988A (ja) 1996-03-13 1997-11-28 Sony Corp 多層配線の形成方法
US6048789A (en) * 1997-02-27 2000-04-11 Vlsi Technology, Inc. IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
US6171957B1 (en) 1997-07-16 2001-01-09 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of semiconductor device having high pressure reflow process
JPH11111845A (ja) * 1997-10-03 1999-04-23 Toshiba Corp 半導体装置及びその製造方法
US6181012B1 (en) 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6355571B1 (en) * 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US6177364B1 (en) * 1998-12-02 2001-01-23 Advanced Micro Devices, Inc. Integration of low-K SiOF for damascene structure
US6242349B1 (en) 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
JP3974284B2 (ja) 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
US6211063B1 (en) * 1999-05-25 2001-04-03 Taiwan Semiconductor Manufacturing Company Method to fabricate self-aligned dual damascene structures
JP4108228B2 (ja) * 1999-07-15 2008-06-25 富士通株式会社 半導体装置の製造方法
US6521532B1 (en) 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6136680A (en) 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6284644B1 (en) * 2000-10-10 2001-09-04 Chartered Semiconductor Manufacturing Ltd. IMD scheme by post-plasma treatment of FSG and TEOS oxide capping layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174019A (ja) * 1998-12-01 2000-06-23 Fujitsu Ltd 半導体装置及びその製造方法
JP2000269337A (ja) * 1999-03-19 2000-09-29 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
US6812127B2 (en) 2004-11-02
KR20020042458A (ko) 2002-06-05
US20020100984A1 (en) 2002-08-01
JP2002164428A (ja) 2002-06-07
TW541657B (en) 2003-07-11

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