KR101005737B1 - 반도체 소자의 금속배선 형성방법 - Google Patents
반도체 소자의 금속배선 형성방법 Download PDFInfo
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- KR101005737B1 KR101005737B1 KR1020030046294A KR20030046294A KR101005737B1 KR 101005737 B1 KR101005737 B1 KR 101005737B1 KR 1020030046294 A KR1020030046294 A KR 1020030046294A KR 20030046294 A KR20030046294 A KR 20030046294A KR 101005737 B1 KR101005737 B1 KR 101005737B1
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
Claims (10)
- 반도체기판을 제공하는 단계;상기 반도체기판 상에 제1 층간절연막을 형성하는 단계;상기 제1 층간절연막 내에 금속 플러그를 형성하는 단계;전체 구조 상부에 확산방지막을 형성하는 단계;상기 확산방지막 상에 제2 층간절연막을 형성하는 단계;상기 금속플러그와 대응하는 상기 제2 층간절연막을 패터닝하여 상기 확산방지막을 오픈시키는 트렌치를 형성하는 단계;상기 트렌치 내측벽에 스페이서를 형성하는 단계;상기 오픈된 확산방지막을 제거하여 그 아래의 상기 제1 층간절연막 및 금속 플러그를 노출시키는 단계;식각 공정을 통해 상기 제1 층간절연막의 일부를 리세스(recess)시켜 상기 금속 플러그의 일측벽을 노출시키는 단계;상기 스페이서를 제거하는 단계; 및상기 노출된 금속 플러그 및 제1 층간절연막을 포함한 상기 트렌치 내부에 상기 트렌치가 매립되도록 금속배선을 형성하는 단계를 포함하는 구성되는 금속배선 형성방법.
- 제 1 항에 있어서,상기 제2 층간절연막은 산화막(SiO2)에 카본(carbon) 이 국부적으로 결합되어 있는 막으로서, BOE 용액에 대한 식각저항을 유도하고, 상기 산화막(SiO2)에 대한 습식식각 선택비를 얻을 수 있도록 형성되는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 제2 층간절연막은 SiOC 구조의 카본 도프트 산화막으로 형성되는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 제2 층간절연막 상에 캡핑층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 금속배선 형성방법.
- 제 4 항에 있어서,상기 캡핑층은 SiON, SiN 또는 SiC 의 물질을 이용하여 100Å 내지 1000Å의 두께로 형성되는 것을 특징으로 하는 금속배선 형성방법.
- 제 4 항에 있어서,상기 캡핑층은 상기 제2 층간절연막의 상부에 대해 O2, CO2 및 N2 처리 중에서, 어느 하나의 처리를 실시하여 SiO2, SiN 또는 SiC 중에서 어느 하나로 형성되는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 트렌치는 건식식각방식을 통해 형성하되, 상기 건식식각 방식은 CxFyHz (1≤x≤5, 1≤y≤8, 1≤z≤3 임) 가스를 주 식각가스로 이용하고, O2, N2, Ar 또는 He 가스를 첨가가스로 이용하는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 스페이서는 LTO(Low Temperature Oxide)로 형성하는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 식각공정은 BOE 용액을 이용하는 것을 특징으로 하는 금속배선 형성방법.
- 제 1 항에 있어서,상기 식각 공정시에, 상기 제1 층간절연막은 50Å 내지 1000Å로 리세스되는 것을 특징으로 하는 금속배선 형성방법.
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KR1020030046294A KR101005737B1 (ko) | 2003-07-09 | 2003-07-09 | 반도체 소자의 금속배선 형성방법 |
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KR1020030046294A KR101005737B1 (ko) | 2003-07-09 | 2003-07-09 | 반도체 소자의 금속배선 형성방법 |
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KR20050006471A KR20050006471A (ko) | 2005-01-17 |
KR101005737B1 true KR101005737B1 (ko) | 2011-01-06 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101476544B1 (ko) * | 2013-03-12 | 2014-12-24 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 개선된 비아 랜딩 프로파일을 위한 신규한 패터닝 방법 |
Families Citing this family (2)
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KR100720532B1 (ko) * | 2005-12-29 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
KR100881826B1 (ko) * | 2007-09-07 | 2009-02-03 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
Citations (4)
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KR20000048191A (ko) * | 1998-12-17 | 2000-07-25 | 가네꼬 히사시 | 반도체 장치 및 그 제조 방법 |
KR20010004644A (ko) * | 1999-06-29 | 2001-01-15 | 윤종용 | 에치 백을 이용한 다결정 실리콘 컨택 플러그 형성방법 및 이를 이용한 반도체 소자의 제조방법 |
KR100278274B1 (ko) | 1997-12-30 | 2001-03-02 | 김영환 | 반도체장치의스택콘택형성방법 |
KR20010054168A (ko) * | 1999-12-03 | 2001-07-02 | 박종섭 | 반도체소자의 콘택홀 및 그 형성방법 |
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- 2003-07-09 KR KR1020030046294A patent/KR101005737B1/ko active IP Right Grant
Patent Citations (4)
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KR100278274B1 (ko) | 1997-12-30 | 2001-03-02 | 김영환 | 반도체장치의스택콘택형성방법 |
KR20000048191A (ko) * | 1998-12-17 | 2000-07-25 | 가네꼬 히사시 | 반도체 장치 및 그 제조 방법 |
KR20010004644A (ko) * | 1999-06-29 | 2001-01-15 | 윤종용 | 에치 백을 이용한 다결정 실리콘 컨택 플러그 형성방법 및 이를 이용한 반도체 소자의 제조방법 |
KR20010054168A (ko) * | 1999-12-03 | 2001-07-02 | 박종섭 | 반도체소자의 콘택홀 및 그 형성방법 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101476544B1 (ko) * | 2013-03-12 | 2014-12-24 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 개선된 비아 랜딩 프로파일을 위한 신규한 패터닝 방법 |
US9312222B2 (en) | 2013-03-12 | 2016-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning approach for improved via landing profile |
US9640435B2 (en) | 2013-03-12 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning approach for improved via landing profile |
US10170420B2 (en) | 2013-03-12 | 2019-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning approach for improved via landing profile |
US10861788B2 (en) | 2013-03-12 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning approach for improved via landing profile |
US11721624B2 (en) | 2013-03-12 | 2023-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Patterning approach for improved via landing profile |
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