CN103811414B - 铜蚀刻集成方法 - Google Patents
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- 238000005530 etching Methods 0.000 title claims abstract description 21
- 229910052802 copper Inorganic materials 0.000 title claims description 13
- 239000010949 copper Substances 0.000 title claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 25
- 239000003989 dielectric material Substances 0.000 claims description 10
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- 238000004519 manufacturing process Methods 0.000 abstract description 8
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- 239000013078 crystal Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 239000005388 borosilicate glass Substances 0.000 description 2
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- 239000005368 silicate glass Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
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Abstract
本发明涉及一种制造互连结构的方法,其中在半导体衬底上方形成牺牲层,然后通过蚀刻牺牲层以形成第一部件。图案化和蚀刻金属层以形成第二部件,然后沉积低k介电材料。该方法允许形成互连结构而不遭遇由多孔低k介电损伤引起的各种问题。
Description
技术领域
本申请总体上涉及半导体领域,更具体地,涉及铜蚀刻集成方法。
背景技术
随着半导体器件的密度的增大和电路元件的尺寸越来越小,电阻电容(RC)延迟时间对电路性能的主导作用在增加。为降低RC延迟效应,我们期望将传统的电介质转换为低k电介质。这些材料具体用作金属间电介质IMD和层间电介质ILD。然而,在加工期间尤其是在用于建立互连的导电材料的加工期间,低k材料会出现其他问题。
发明内容
为解决上述问题,本发明提供了一种用于形成互连结构的方法,包括:在具有导电区的半导体衬底上方沉积牺牲层,并且所述牺牲层覆盖所述导电区;在所述牺牲层上方沉积硬掩模层;图案化所述硬掩模层并且蚀刻穿过所述硬掩模层和所述牺牲层,以形成被所述牺牲层中的开口限定的第一部件;在所述第一部件上方沉积金属层并且填充所述开口,以在所述开口中形成金属体,所述金属体由所述金属层的下部限定;图案化和蚀刻所述金属层的上部以形成第二部件,所述第二部件在所述金属层的上部中具有第一凹槽并且由从所述金属体延伸的垂直凸起限定;去除所述牺牲层以露出所述金属体的相对侧壁并且在所述相对侧壁周围形成第二凹槽;在所述垂直凸起的上表面上方沉积低k介电材料并且填充所述第一凹槽和所述第二凹槽;以及去除过量的介电层并且露出所述垂直凸起的上表面。
其中,所述金属层包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
该方法进一步包括:形成阻挡层,所述阻挡层覆盖并且包围所述金属体和所述垂直凸起。
其中,所述第一部件包括沟槽,并且所述第二部件包括通孔。
其中,所述金属体包括成角的相对侧壁,所述相对侧壁逐渐靠近以形成具有较宽顶部和较窄底部的金属体。
其中,所述牺牲层包括聚酰亚胺或者聚(新戊基甲基丙烯酸酯-乙二醇二甲基丙烯酸酯共聚物)。
其中,通过大于200C的温度的退火来形成所述阻挡层。
该方法进一步包括:在所述通孔上方形成额外的金属层并且电连接至所述通孔。
其中,所述硬掩模层是包括氮化物、碳化物或者氧化物的介电硬掩模层。
该方法进一步包括:在所述低k介电材料内以及相邻金属体的成角侧壁之间形成至少一个气隙。
此外,还提供了一种用于形成铜互连结构的方法,包括:提供半导体衬底;在所述半导体衬底上方形成牺牲层;在所述牺牲层上方形成介电硬掩模层;通过蚀刻所述硬掩模层和所述牺牲层来实施第一蚀刻,以在所述牺牲层的开口中形成第一部件;在所述牺牲层上方形成金属层并且填充所述部件开口;通过蚀刻所述金属层来实施第二蚀刻以形成第二部件;去除所述牺牲层;在所述第一部件和所述第二部件上方沉积低k介电材料;在所述低k介电材料内形成至少一个气隙;以及去除过量的介电层。
其中,所述气隙是自成型的。
其中,所述低k介电材料具有小于约3的介电常数。
该方法进一步包括:在所述第一部件、所述第二部件和所述低k介电材料之间形成阻挡层,并且所述阻挡层是连续的。
其中,所述金属层包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
此外,还提供了一种集成电路,包括至少两个邻近的互连结构,所述互连结构包括:具有成角的相对侧壁的金属体和从所述金属体延伸的金属垂直凸起;低k介电材料,设置在所述邻近的互连结构的上方和之间并且形成介电区;以及阻挡层,位于所述介电材料和所述互连结构之间。
其中,至少一个气隙设置在所述互连结构的成角侧壁之间的所述介电区内。
其中,所述阻挡层形成连续层以包围所述金属体的相对侧壁和从所述金属体延伸的垂直凸起。
其中,所述金属体和所述垂直凸起的金属包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
其中,所述成角的相对侧壁逐渐靠近以形成具有较宽顶部和较窄底部的金属体。
附图说明
图1A至图1M是根据本发明示出形成互连结构的一个实施例的步骤的局部截面图。
图2示出了根据本发明用于制造互连结构的方法的一些实施例的流程图。
具体实施方式
参考附图所作的描述,其中相同的编号通常用于表示相同的元件,并且其中各种结构不必按比例绘制。在以下描述中,为便于理解,以下阐述了用于说明目的的许多具体细节。然而,可以用这些具体细节的较少部分来实施本文所描述的一个或多个方面,这对于本领域技术人员来说将是显而易见的。在其他情况下,框图中示出已知的结构和器件以帮助理解。
使用许多不同的加工步骤在半导体晶圆上加工或者制造半导体器件从而生产晶体管和互连元件。为电连接与半导体晶圆相关联的晶体管端子,在介电材料中形成导电(例如,金属)沟槽、通孔等作为半导体器件的一部分。沟槽和通孔连接晶体管、半导体器件的内部电路和半导体器件外部的电路之间的电信号和电源。
在形成互连元件的过程中,半导体晶圆可能经历例如掩蔽、蚀刻和沉积工艺以形成期望的半导体器件电路。具体来说,可以实施多个掩蔽和蚀刻步骤以在诸如低k介电层的介电层中形成凹进区域的图案,介电层位于充当互连件的沟槽和通孔的半导体晶圆上。然后可以实施沉积工艺以在半导体晶圆上方沉积金属层从而在沟槽和通孔中以及半导体晶圆的非凹进区域上沉积金属。为了隔离诸如图案化的沟槽和通孔的互连,将半导体晶圆非凹进区域上沉积的金属去除。
随着集成电路器件按比例缩小,日益需要低k层以降低信号延迟和功率损失的影响。一种已经完成的方法是将多孔和掺杂物引入介电绝缘层中。
因此,对较低介电常数材料的需求导致数种不同类型的有机和无机低k材料的开发。具体来说,由于半导体部件尺寸减小到小于0.13微米,所以介电常数小于约3.0的低k材料的结合成为了标准惯例。当部件尺寸减小到小于0.13微米时,例如65nm或者以下,需要介电常数小于约2.5的材料。已经开发出并且建议用于半导体器件中的数种不同的有机和无机低k材料作为具有介电常数介于约2.2和约3.0之间范围内的绝缘材料。
然而,因为低k介电材料硬度较低、化学稳定性差或者更多孔隙或者这些因素的组合,所以它们易于受到来自蚀刻工艺的损伤。等离子体损伤可以表现为更高的漏电流、较低的击穿电压和与低k介电材料相关的介电常数的变化。
因此,需要集成电路制造技术使制造工艺发展,凭借制造工艺可以在不遭遇多孔低k介电层引发的各种问题的情况下形成互连结构从而提高集成电路器件的产量、性能和可靠性。
因此,本发明涉及一种制造互连结构的方法。该方法提供了用于限定互连结构的工艺,该互连结构消除了蚀刻工艺期间引起的低k介电损伤。该工艺提供了进一步的优点,即排除了使用蚀刻终止或者NFARC(无氮抗反射涂层)层的必要性,从而使该工艺具有更高的成本效益。
图1A至图1K示出了根据本发明处于制造工艺各阶段中形成互连结构的方法的一个实施例的多个局部截面图。参考图1A,提供了具有导电区103的半导体衬底102。衬底102被理解为包括半导体晶圆或者衬底,由诸如硅或锗或者绝缘体上硅结构(SOI)的半导体材料形成。半导体结构可以进一步包括一层或者多层导电层(诸如金属或硅)和/或绝缘层,以及形成在衬底中或上方的一个或多个有源或者无源器件等,例如显示衬底,诸如液晶显示器(LCD)、等离子体显示器、电荧光(EL)灯显示器或者发光二极管(LED)衬底。
牺牲层104位于衬底102上方并且覆盖导电区103。牺牲层104包括均聚物或者共聚物。在一个实施例中,牺牲层104包括一层或者多层聚酰亚胺或者聚(新戊基甲基丙烯酸酯-乙二醇二甲基丙烯酸酯共聚物,P(neopentylmethacrylate-co-ethyleneglycoldimethacryalte))(聚(npMAco-EGDA))。通过一个或者多个化学汽相沉积(CVD)或者旋涂工艺来沉积牺牲层104。牺牲层的厚度将是从约10000°A(埃)至约100°A的范围。
如图1B所示,然后通过例如CVD工艺沉积106介电硬掩模层108。介电硬掩模层108用于在后续的光刻工艺中图案化牺牲层104。在一些实施例中,介电硬掩模层108包括诸如氧化硅、氮化硅、氮氧化硅和碳化硅的一种材料。介电硬掩模层108将具有约1000°A至约10°A范围的厚度。
如图1C所示,在沉积硬掩模层108之后,在一个实施例中,通过工艺110在硬掩模层108上方形成光刻胶膜112。可以使用常规的光刻胶材料。光刻胶膜112可以是含碳的有机材料。可以使用具有不同厚度的各种光刻胶。图1D中实施了光刻胶图案化和蚀刻114。
如图1E所示,然后实施图案化硬掩模108和穿过硬掩模层108至牺牲层104的第一蚀刻工艺116,从而去除牺牲层104的一部分并且形成由介电层104中的开口118限定的第一部件。在一个实施例中,第一部件包括沟槽。
图1F中,将金属层124沉积122在第一部件上方并且填充介电层104中的开口118以形成其中的金属体125。通过金属层124的下部124(a)来限定金属体125。金属体包括成角的相对侧壁。在一个实施例中,金属层124可以由诸如Al、W、Cu的元素或者CuMn、CuTi、CuCr或者CuNb等形成。除此之外,可以使用例如等离子体汽相沉积技术来形成金属层124。在一个实施例中,金属层124可以沉积为约100°A(埃)至约20000°A范围的厚度。
如图1G所示,在金属层124上方形成光刻胶膜112’并且通过常规技术对其进行图案化126。如图1H所示,实施第二蚀刻128以图案化和蚀刻金属层124的上部124(b)从而形成具有第一凹槽123(a)、123(b)以及被从金属体125延伸的垂直凸起127限定的第二部件。垂直凸起127包括相对侧壁129(a)、129(b)和上表面130。在一个实施例中,第二部件包括通孔。
在图1I中,例如通过一个或者多个蚀刻、湿式剥离、热处理、UV或者IR辐射技术(未示出)来去除牺牲层104。牺牲层104的去除露出了金属体125的成角的相对侧壁132(a)、132(b)并且形成第二凹槽131(a)、131(b)。锥形化成角的相对侧壁132(a)、132(b)从而使得金属体125具有较宽的顶部125(a)和较窄的底部125(b)。
在一个实施例中,阻挡层134形成在金属体125和垂直凸起127上方并且包围金属体125和垂直凸起127,并且阻挡层134设置在介电材料136(图1K)和金属层124之间。通过包围金属体125和垂直凸起127,形成连续的阻挡层134。通过沉积介电材料例如氮化硅和碳化硅来形成阻挡层134。在一个实施例中,通过沉积金属例如TiN、TaN、Co、WN、TiSiN、TaSiN或者它们的组合来形成阻挡层134。如图1J所示,在另一个实施例中,在大于约200℃的温度下实施热处理135,从而自成型阻挡层134。在一个实施例中,阻挡层134的厚度可以是从约1°A(埃)至约300°A的范围。
在图1K中,通过工艺137沉积低k介电材料136以填充第一123(a)、123(b)凹槽和第二131(a)、131(b)凹槽并且覆盖垂直凸起127的上表面130以形成介电区136’。因此,低k介电材料136封装垂直凸起127和金属体125。低k电介质包括k值小于约3的电介质。这些电介质包括例如碳掺杂的二氧化硅,还被称为有机硅酸盐玻璃(OSG)和氧化碳。低k材料还可以包括硼磷硅酸盐玻璃(BPSG)、硼硅酸盐玻璃(BSG)和磷硅酸盐玻璃(PSG)等。可以使用例如四乙基原硅酸盐(TEOS)、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、低压CVD(LPCVD)或者旋涂技术来形成介电层134。在一个实施例中,低k电介质的厚度将是从约100°A至约20000°A的范围。
在图1K示出的实施例中,在介电材料136内形成至少一个气隙138。气隙138设置在邻近金属体125的成角的侧壁132(a)、132(b)之间的介电区136’中。在低k材料136的沉积期间可以自成型气隙138。在一个实施例中,气隙的尺寸可以是从约0°A至约20000°A的范围。然而,预期可以通过低k材料136沉积工艺来控制气隙的尺寸。如图1L所示,然后可以实施化学机械抛光(CMP)工艺138以去除过量的介电层136并且露出垂直凸起127的上表面130。
如图1M所示,在CMP工艺之后,可以重复该方法以形成互连结构152的额外的金属层150,该互连结构位于通孔上方并且与通孔电连接,从而形成至少两个邻近的互连结构的集成电路100’。
图2示出了根据本发明的一个实施例用于形成半导体结构的方法200的一些实施例的流程图。虽然以下示出并且描述了作为一系列行为或者事件的方法200,但是应该理解,示出的这些行为或者事件的顺序不能用于限制性解释。例如,一些行为可以以不同的顺序和/或与本文示出和/或描述的其他行为或者事件同时发生。此外,并不需要示出的所有行为来实施本文说明书实施例的一个或者多个方面。而且,可以以一个或者多个分离的行为和/或阶段来实施本文所描述的一个或者多个行为。
步骤202中,提供半导体衬底。步骤204中,然后在衬底上方形成牺牲层。
步骤206中,在牺牲层上方沉积硬掩模层。
步骤208中,通过图案化和蚀刻穿过硬掩模和牺牲层以在牺牲层中形成开口,从而形成第一部件。
步骤210中,在第一部件上方沉积金属层并且金属层填充部件开口。
步骤212中,图案化并且蚀刻金属层的上部以形成第二部件。
步骤214中,去除牺牲层。
步骤216中,通过CVD、PVD、MOCVD或者ALD形成阻挡层,或者可以通过热处理自成型阻挡层。
步骤218中,沉积低k介电材料以填充凹槽并且包围金属体和垂直凸起。
步骤220中,在低k介电材料中形成至少一个气隙。该气隙设置在邻近的互连结构之间的介电区中。
步骤222中,实施CMP工艺以去除过量的介电层并且露出垂直凸起的顶面。然后该方法结束。
应该理解,基于对说明书和附图的阅读和/或理解,本领域普通技术人员可以想到等同的更改和/或修改。本发明包括所有的这些修改和更改,通常不用于限制。此外,虽然就数个实施例中的一个仅公开一个具体部件或者方面,但是正如期望的,这个部件或者方面可以与其他实施例的一个或多个其他部件和/或方面结合。而且,就本文中使用的术语“包括”、“具有”、“有”、“带有”和/或它们的派生词来说,这些术语用于表示涵盖,类似“包括”的含义。再者,“示例的”仅意味着一个实例,而不表示最好的。还应该理解,为简明和易于理解的目的,用相对于另一个的具体规格和/或方位来示出本文中所描述的部件、层和/或元件,然而,实际规格和/或方位可以与本文所示出的不同。
因此,本发明涉及用于形成互连结构的方法,包括在牺牲层上方形成硬掩模层。该方法进一步包括图案化硬掩模层和牺牲层以形成由牺牲层中的开口限定的第一部件。该方法进一步包括在第一部件上方沉积金属层并且金属层填充开口以形成金属体,该金属体被金属层的下部限定。该方法进一步包括图案化和蚀刻金属层的上部以在金属层的上部中形成具有第一凹槽并且被从金属体延伸的垂直凸起限定的第二部件。该方法进一步包括去除牺牲层以露出金属体的相对侧壁以及形成邻近相对侧壁的第二凹槽,然后在垂直凸起的上表面上方沉积低k介电材料并且低k介电材料填充第一凹槽和第二凹槽。
本发明进一步涉及一种用于形成铜互连结构的方法,包括提供具有导电区的半导体衬底和在衬底上方形成牺牲层。该方法进一步包括在牺牲层上方形成介电掩模层。该方法进一步包括通过蚀刻硬掩模层和牺牲层来实施第一蚀刻以形成牺牲层中开口的第一部件。该方法进一步包括在牺牲层上方沉积金属层并且金属层填充该部件开口。该方法进一步包括通过蚀刻金属层来实施第二蚀刻以形成第二部件以及去除牺牲层。该方法进一步包括在第一部件和第二部件上方沉积低k介电材料并且在低k介电材料内形成至少一个气隙。
本发明进一步涉及集成电路,包括至少两个邻近的互连结构。该互连结构包括具有成角的相对侧壁的金属体和从金属体延伸的金属垂直凸起。该集成电路进一步包括设置在邻近的互连结构上方和之间的低k介电材料。该电路进一步包括位于介电材料和互连结构之间的阻挡层。
Claims (20)
1.一种用于形成互连结构的方法,包括:
在具有导电区的半导体衬底上方沉积牺牲层,并且所述牺牲层覆盖所述导电区;
在所述牺牲层上方沉积硬掩模层;
图案化所述硬掩模层并且蚀刻穿过所述硬掩模层和所述牺牲层,以形成被所述牺牲层中的开口限定的第一部件;
在所述第一部件上方沉积金属层并且填充所述开口,以在所述开口中形成金属体,所述金属体由所述金属层的下部限定;
图案化和蚀刻所述金属层的上部以形成第二部件,所述第二部件在所述金属层的上部中具有第一凹槽并且由从所述金属体延伸的垂直凸起限定;
去除所述牺牲层以露出所述金属体的相对侧壁并且在所述相对侧壁周围形成第二凹槽;
在所述垂直凸起的上表面上方沉积低k介电材料并且填充所述第一凹槽和所述第二凹槽;以及
去除过量的介电层并且露出所述垂直凸起的上表面。
2.根据权利要求1所述的方法,其中,所述金属层包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
3.根据权利要求1所述的方法,进一步包括:形成阻挡层,所述阻挡层覆盖并且包围所述金属体和所述垂直凸起。
4.根据权利要求1所述的方法,其中,所述第一部件包括沟槽,并且所述第二部件包括通孔。
5.根据权利要求2所述的方法,其中,所述金属体包括成角的相对侧壁,所述相对侧壁逐渐靠近以形成具有较宽顶部和较窄底部的金属体。
6.根据权利要求2所述的方法,其中,所述牺牲层包括聚酰亚胺或者聚(新戊基甲基丙烯酸酯-乙二醇二甲基丙烯酸酯共聚物)。
7.根据权利要求3所述的方法,其中,通过大于200℃的温度的退火来形成所述阻挡层。
8.根据权利要求4所述的方法,进一步包括:在所述通孔上方形成额外的金属层并且电连接至所述通孔。
9.根据权利要求6所述的方法,其中,所述硬掩模层是包括氮化物、碳化物或者氧化物的介电硬掩模层。
10.根据权利要求1所述的方法,进一步包括:在所述低k介电材料内以及相邻金属体的成角侧壁之间形成至少一个气隙。
11.一种用于形成铜互连结构的方法,包括:
提供半导体衬底;
在所述半导体衬底上方形成牺牲层;
在所述牺牲层上方形成介电硬掩模层;
通过蚀刻所述硬掩模层和所述牺牲层来实施第一蚀刻,以在所述牺牲层的开口中形成第一部件;
在所述牺牲层上方形成金属层并且填充所述部件开口;
通过蚀刻所述金属层来实施第二蚀刻以形成第二部件,其中,所述第二部件包括垂直凸起和所述垂直凸起两侧的凹槽,所述垂直凸起从金属体延伸并且位于所述金属体之上,所述金属体宽于所述垂直凸起;
去除所述牺牲层;
在所述第一部件和所述第二部件上方沉积低k介电材料;
在所述低k介电材料内形成至少一个气隙;以及
去除过量的介电层。
12.根据权利要求11所述的方法,其中,所述气隙是自成型的。
13.根据权利要求11所述的方法,其中,所述低k介电材料具有小于3的介电常数。
14.根据权利要求13所述的方法,进一步包括:在所述第一部件、所述第二部件和所述低k介电材料之间形成阻挡层,并且所述阻挡层是连续的。
15.根据权利要求14所述的方法,其中,所述金属层包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
16.一种集成电路,包括至少两个邻近的互连结构,所述互连结构包括:
具有成角的相对侧壁的金属体和从所述金属体延伸的金属垂直凸起,所述金属体宽于所述金属垂直凸起;
低k介电材料,设置在所述邻近的互连结构的上方和之间并且形成介电区;以及
阻挡层,位于所述介电材料和所述互连结构之间。
17.根据权利要求16所述的集成电路,其中,至少一个气隙设置在所述互连结构的成角侧壁之间的所述介电区内。
18.根据权利要求16所述的集成电路,其中,所述阻挡层形成连续层以包围所述金属体的相对侧壁和从所述金属体延伸的垂直凸起。
19.根据权利要求16所述的集成电路,其中,所述金属体和所述垂直凸起的金属包括Al、W、Cu、CuMn、CuTi、CuV、CuCr或者CuNb。
20.根据权利要求16所述的集成电路,其中,所述成角的相对侧壁逐渐靠近以形成具有较宽顶部和较窄底部的金属体。
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