JP2000048567A5 - - Google Patents
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- Publication number
- JP2000048567A5 JP2000048567A5 JP1998252893A JP25289398A JP2000048567A5 JP 2000048567 A5 JP2000048567 A5 JP 2000048567A5 JP 1998252893 A JP1998252893 A JP 1998252893A JP 25289398 A JP25289398 A JP 25289398A JP 2000048567 A5 JP2000048567 A5 JP 2000048567A5
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory cell
- signal
- address signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims 2
- 230000004913 activation Effects 0.000 description 9
- 230000000295 complement effect Effects 0.000 description 6
- 102100032530 Glypican-3 Human genes 0.000 description 3
- 101001014668 Homo sapiens Glypican-3 Proteins 0.000 description 3
- 208000003874 Simpson-Golabi-Behmel syndrome Diseases 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 101100438168 Arabidopsis thaliana CAD9 gene Proteins 0.000 description 2
- 101100494469 Dictyostelium discoideum cadA gene Proteins 0.000 description 2
- 101100178218 Schizosaccharomyces pombe (strain 972 / ATCC 24843) hmt2 gene Proteins 0.000 description 2
- 101150018983 cad1 gene Proteins 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10252893A JP2000048567A (ja) | 1998-05-22 | 1998-09-07 | 同期型半導体記憶装置 |
| US09/246,726 US6134179A (en) | 1998-05-22 | 1999-02-09 | Synchronous semiconductor memory device capable of high speed reading and writing |
| KR1019990014720A KR100306857B1 (ko) | 1998-05-22 | 1999-04-24 | 독출 및 기록을 고속으로 행하는 동기형 반도체 기억 장치 |
| US09/593,957 US6272066B1 (en) | 1998-05-22 | 2000-06-15 | Synchronous semiconductor memory device capable of high speed reading and writing |
| US09/882,037 US6473360B2 (en) | 1998-05-22 | 2001-06-18 | Synchronous semiconductor memory device capable of high speed reading and writing |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14162198 | 1998-05-22 | ||
| JP10-141621 | 1998-05-22 | ||
| JP10252893A JP2000048567A (ja) | 1998-05-22 | 1998-09-07 | 同期型半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000048567A JP2000048567A (ja) | 2000-02-18 |
| JP2000048567A5 true JP2000048567A5 (enExample) | 2005-11-04 |
Family
ID=26473825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10252893A Pending JP2000048567A (ja) | 1998-05-22 | 1998-09-07 | 同期型半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (3) | US6134179A (enExample) |
| JP (1) | JP2000048567A (enExample) |
| KR (1) | KR100306857B1 (enExample) |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3706772B2 (ja) * | 1999-07-12 | 2005-10-19 | 富士通株式会社 | 半導体集積回路 |
| JP2001067866A (ja) | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| JP4427847B2 (ja) * | 1999-11-04 | 2010-03-10 | エルピーダメモリ株式会社 | ダイナミック型ramと半導体装置 |
| JP4588158B2 (ja) * | 2000-03-28 | 2010-11-24 | 富士通セミコンダクター株式会社 | 半導体集積回路 |
| JP4524439B2 (ja) * | 2000-03-30 | 2010-08-18 | ラウンド ロック リサーチ、エルエルシー | ゼロレイテンシ機能、ゼロバスターンアラウンド機能を有するシンクロナスフラッシュメモリ |
| JP4600792B2 (ja) * | 2000-07-13 | 2010-12-15 | エルピーダメモリ株式会社 | 半導体装置 |
| KR100359778B1 (ko) * | 2000-07-19 | 2002-11-04 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 어드레스 발생 회로 |
| JP4569915B2 (ja) * | 2000-08-11 | 2010-10-27 | エルピーダメモリ株式会社 | 半導体記憶装置 |
| KR100374641B1 (ko) * | 2000-11-24 | 2003-03-04 | 삼성전자주식회사 | 스탠바이 모드에서 지연동기 루프회로의 전력소모를감소시키기 위한 제어회로를 구비하는 반도체 메모리장치및 이의 파우워 다운 제어방법 |
| KR100380409B1 (ko) * | 2001-01-18 | 2003-04-11 | 삼성전자주식회사 | 반도체 메모리 소자의 패드배열구조 및 그의 구동방법 |
| US6480429B2 (en) | 2001-02-12 | 2002-11-12 | Micron Technology, Inc. | Shared redundancy for memory having column addressing |
| US7003643B1 (en) | 2001-04-16 | 2006-02-21 | Micron Technology, Inc. | Burst counter controller and method in a memory device operable in a 2-bit prefetch mode |
| KR100772092B1 (ko) * | 2001-06-29 | 2007-11-01 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| WO2003009301A1 (en) * | 2001-07-17 | 2003-01-30 | Mitsubishi Denki Kabushiki Kaisha | Storage device |
| KR100438778B1 (ko) * | 2001-11-07 | 2004-07-05 | 삼성전자주식회사 | 웨이브 파이프라인 구조를 갖는 동기식 반도체 메모리장치및 웨이브 파이프라인 제어방법 |
| JP4111486B2 (ja) * | 2002-01-31 | 2008-07-02 | シャープ株式会社 | 半導体記憶装置および電子情報機器 |
| US6678200B2 (en) * | 2002-05-14 | 2004-01-13 | Hewlett-Packard Development Company, Lp. | Systems and methods for communicating with memory blocks |
| GB2409776B (en) * | 2002-05-14 | 2005-10-12 | Hewlett Packard Co | Systems and methods for communicating with memory blocks |
| JP4134637B2 (ja) * | 2002-08-27 | 2008-08-20 | 株式会社日立製作所 | 半導体装置 |
| KR100465602B1 (ko) * | 2002-09-10 | 2005-01-13 | 주식회사 하이닉스반도체 | 글로벌 입출력(gio) 라인에 리피터를 구비하는 반도체메모리 장치 |
| US7035150B2 (en) * | 2002-10-31 | 2006-04-25 | Infineon Technologies Ag | Memory device with column select being variably delayed |
| CN100437823C (zh) * | 2003-04-23 | 2008-11-26 | 富士通株式会社 | 半导体存储装置 |
| KR100499417B1 (ko) * | 2003-07-15 | 2005-07-05 | 주식회사 하이닉스반도체 | 디디알 에스디램에서의 링잉 현상 방지 방법 및 그 장치 |
| US6956786B2 (en) * | 2003-12-04 | 2005-10-18 | Infineon Technologies North America Corp. | Random access memory with optional inaccessible memory cells |
| KR100618697B1 (ko) * | 2004-04-28 | 2006-09-08 | 주식회사 하이닉스반도체 | 메모리 장치의 데이타 전송 라인의 구조 |
| US7084686B2 (en) * | 2004-05-25 | 2006-08-01 | Micron Technology, Inc. | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal |
| US7078951B2 (en) * | 2004-08-27 | 2006-07-18 | Micron Technology, Inc. | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal |
| KR100618704B1 (ko) * | 2004-12-20 | 2006-09-08 | 주식회사 하이닉스반도체 | 메모리 장치의 mrs 설정동작 제어 방법 |
| US7177208B2 (en) * | 2005-03-11 | 2007-02-13 | Micron Technology, Inc. | Circuit and method for operating a delay-lock loop in a power saving manner |
| JP4982711B2 (ja) * | 2005-03-31 | 2012-07-25 | エスケーハイニックス株式会社 | 高速動作のためのメモリチップ構造 |
| KR100724333B1 (ko) * | 2005-10-05 | 2007-06-04 | 삼성전자주식회사 | 리던던시 플래그 신호의 응답마진이 향상되는 반도체메모리 장치 및 이를 이용한 리던던시 구동 방법 |
| JP4828203B2 (ja) * | 2005-10-20 | 2011-11-30 | エルピーダメモリ株式会社 | 同期型半導体記憶装置 |
| US7505349B2 (en) * | 2006-09-07 | 2009-03-17 | Honeywell International Inc. | Refresh sequence control for multiple memory elements |
| US7554864B2 (en) * | 2007-03-27 | 2009-06-30 | Hynix Semiconductor Inc. | Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits |
| KR100907008B1 (ko) * | 2007-12-21 | 2009-07-08 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그의 데이터 마스킹 방법 |
| KR100958806B1 (ko) | 2008-09-01 | 2010-05-24 | 주식회사 하이닉스반도체 | 데이터 송수신 회로 및 제어 방법 |
| KR101154001B1 (ko) * | 2009-11-12 | 2012-06-08 | 에스케이하이닉스 주식회사 | 어드레스제어회로 및 반도체메모리장치 |
| JP5538958B2 (ja) * | 2010-03-05 | 2014-07-02 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
| JP5314640B2 (ja) * | 2010-06-21 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR101198138B1 (ko) * | 2010-10-29 | 2012-11-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
| US9350386B2 (en) | 2012-04-12 | 2016-05-24 | Samsung Electronics Co., Ltd. | Memory device, memory system, and method of operating the same |
| US9715909B2 (en) * | 2013-03-14 | 2017-07-25 | Micron Technology, Inc. | Apparatuses and methods for controlling data timing in a multi-memory system |
| US9111624B2 (en) | 2013-03-22 | 2015-08-18 | Katsuyuki Fujita | Semiconductor memory device |
| KR102407184B1 (ko) * | 2017-10-31 | 2022-06-10 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 이를 포함하는 반도체 시스템 |
| KR102685463B1 (ko) * | 2019-03-12 | 2024-07-17 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| TWI762852B (zh) * | 2020-01-03 | 2022-05-01 | 瑞昱半導體股份有限公司 | 記憶體裝置及其操作方法 |
| EP4095694A4 (en) * | 2020-02-24 | 2022-12-14 | Huawei Technologies Co., Ltd. | MEMORY, CHIP AND METHOD OF STORING REPAIR INFORMATION OF A MEMORY |
| IT202000016441A1 (it) | 2020-07-07 | 2022-01-07 | Sk Hynix Inc | Comparatore di risorse di ridondanza per una architettura di bus, architettura di bus per un dispositivo di memoria che implementa un metodo migliorato di confronto e corrispondente metodo di confronto |
| DE102021202376A1 (de) | 2021-03-11 | 2022-09-15 | Infineon Technologies Ag | Datenspeichervorrichtung und Verfahren zum Schreiben von Informationen in eine Datenspeichervorrichtung |
| CN116230048B (zh) * | 2021-12-06 | 2025-11-21 | 长鑫存储技术有限公司 | 地址刷新电路、方法、存储器和电子设备 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6432489A (en) * | 1987-07-27 | 1989-02-02 | Matsushita Electronics Corp | Memory device |
| US5034962A (en) * | 1988-07-01 | 1991-07-23 | Oki Electric Industry Co., Ltd. | Voice-band signal processor |
| US5323426A (en) * | 1992-02-21 | 1994-06-21 | Apple Computer, Inc. | Elasticity buffer for data/clock synchronization |
| JP2763080B2 (ja) * | 1992-03-18 | 1998-06-11 | 富士通株式会社 | 光ディスク装置 |
| JPH07140207A (ja) * | 1993-11-15 | 1995-06-02 | Hitachi Ltd | 半導体装置及びその試験方法 |
| JP2914171B2 (ja) * | 1994-04-25 | 1999-06-28 | 松下電器産業株式会社 | 半導体メモリ装置およびその駆動方法 |
| US5513144A (en) * | 1995-02-13 | 1996-04-30 | Micron Technology, Inc. | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
| KR0172396B1 (ko) * | 1995-10-31 | 1999-03-30 | 김광호 | 반도체 메모리장치의 워드라인 구동방법 |
| US5587961A (en) * | 1996-02-16 | 1996-12-24 | Micron Technology, Inc. | Synchronous memory allowing early read command in write to read transitions |
| KR100205009B1 (ko) * | 1996-04-17 | 1999-06-15 | 윤종용 | 비디오신호 변환장치 및 그 장치를 구비한 표시장치 |
| US5982697A (en) * | 1996-12-02 | 1999-11-09 | Micron Technology, Inc. | Method for initializing and reprogramming a control operation feature of a memory device |
| KR100253564B1 (ko) * | 1997-04-25 | 2000-05-01 | 김영환 | 고속 동작용 싱크로노스 디램 |
| JPH1116349A (ja) * | 1997-06-26 | 1999-01-22 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
-
1998
- 1998-09-07 JP JP10252893A patent/JP2000048567A/ja active Pending
-
1999
- 1999-02-09 US US09/246,726 patent/US6134179A/en not_active Expired - Lifetime
- 1999-04-24 KR KR1019990014720A patent/KR100306857B1/ko not_active Expired - Fee Related
-
2000
- 2000-06-15 US US09/593,957 patent/US6272066B1/en not_active Expired - Lifetime
-
2001
- 2001-06-18 US US09/882,037 patent/US6473360B2/en not_active Expired - Fee Related
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