IL121955A - Method and apparatus for design verification - Google Patents

Method and apparatus for design verification

Info

Publication number
IL121955A
IL121955A IL12195597A IL12195597A IL121955A IL 121955 A IL121955 A IL 121955A IL 12195597 A IL12195597 A IL 12195597A IL 12195597 A IL12195597 A IL 12195597A IL 121955 A IL121955 A IL 121955A
Authority
IL
Israel
Prior art keywords
design verification
verification
design
Prior art date
Application number
IL12195597A
Other languages
English (en)
Other versions
IL121955A0 (en
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of IL121955A0 publication Critical patent/IL121955A0/xx
Publication of IL121955A publication Critical patent/IL121955A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Tests Of Electronic Circuits (AREA)
IL12195597A 1996-10-17 1997-10-13 Method and apparatus for design verification IL121955A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/733,352 US5841967A (en) 1996-10-17 1996-10-17 Method and apparatus for design verification using emulation and simulation

Publications (2)

Publication Number Publication Date
IL121955A0 IL121955A0 (en) 1998-03-10
IL121955A true IL121955A (en) 2000-12-06

Family

ID=24947260

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12195597A IL121955A (en) 1996-10-17 1997-10-13 Method and apparatus for design verification

Country Status (8)

Country Link
US (2) US5841967A (fr)
EP (1) EP0838772A3 (fr)
JP (2) JP3131177B2 (fr)
KR (1) KR100483636B1 (fr)
CA (1) CA2218458C (fr)
IL (1) IL121955A (fr)
SG (1) SG54583A1 (fr)
TW (1) TW464828B (fr)

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JPH10171847A (ja) 1998-06-26
SG54583A1 (en) 1998-11-16
CA2218458A1 (fr) 1998-04-17
IL121955A0 (en) 1998-03-10
KR100483636B1 (ko) 2005-06-16
EP0838772A3 (fr) 1998-05-13
JP3131177B2 (ja) 2001-01-31
KR19980032933A (ko) 1998-07-25
CA2218458C (fr) 2005-12-06
TW464828B (en) 2001-11-21
US6058492A (en) 2000-05-02
JP2001060219A (ja) 2001-03-06
EP0838772A2 (fr) 1998-04-29
US5841967A (en) 1998-11-24

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