GB1595548A - Method for preparing a substrate surface of and a method of making a semiconductor device - Google Patents

Method for preparing a substrate surface of and a method of making a semiconductor device Download PDF

Info

Publication number
GB1595548A
GB1595548A GB19043/80A GB1904380A GB1595548A GB 1595548 A GB1595548 A GB 1595548A GB 19043/80 A GB19043/80 A GB 19043/80A GB 1904380 A GB1904380 A GB 1904380A GB 1595548 A GB1595548 A GB 1595548A
Authority
GB
United Kingdom
Prior art keywords
layer
oxide
angstroms
portions
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB19043/80A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of GB1595548A publication Critical patent/GB1595548A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10P14/61—
    • H10P76/40—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
GB19043/80A 1977-01-26 1978-01-25 Method for preparing a substrate surface of and a method of making a semiconductor device Expired GB1595548A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76239877A 1977-01-26 1977-01-26

Publications (1)

Publication Number Publication Date
GB1595548A true GB1595548A (en) 1981-08-12

Family

ID=25064929

Family Applications (5)

Application Number Title Priority Date Filing Date
GB19043/80A Expired GB1595548A (en) 1977-01-26 1978-01-25 Method for preparing a substrate surface of and a method of making a semiconductor device
GB32523/79A Expired GB1595545A (en) 1977-01-26 1978-01-25 Method for forming high definition layers in a semiconductor device
GB32524/79A Expired GB1595546A (en) 1977-01-26 1978-01-25 Method for making a semiconductor device
GB3022/78A Expired GB1595543A (en) 1977-01-26 1978-01-25 Memory cell
GB32525/79A Expired GB1595547A (en) 1977-01-26 1978-01-25 Method for forming very small contact windows in a semiconductor device

Family Applications After (4)

Application Number Title Priority Date Filing Date
GB32523/79A Expired GB1595545A (en) 1977-01-26 1978-01-25 Method for forming high definition layers in a semiconductor device
GB32524/79A Expired GB1595546A (en) 1977-01-26 1978-01-25 Method for making a semiconductor device
GB3022/78A Expired GB1595543A (en) 1977-01-26 1978-01-25 Memory cell
GB32525/79A Expired GB1595547A (en) 1977-01-26 1978-01-25 Method for forming very small contact windows in a semiconductor device

Country Status (5)

Country Link
JP (10) JPS5394190A (enExample)
DE (1) DE2802048A1 (enExample)
FR (5) FR2382768A1 (enExample)
GB (5) GB1595548A (enExample)
IT (1) IT1089299B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS6055988B2 (ja) 1979-01-26 1985-12-07 株式会社日立製作所 半導体装置の製法
JPS5713772A (en) * 1980-06-30 1982-01-23 Hitachi Ltd Semiconductor device and manufacture thereof
DE3032632A1 (de) 1980-08-29 1982-04-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung integrierter dynamischer ram-eintransistor-speicherzellen
CN1049070C (zh) 1994-06-08 2000-02-02 现代电子产业株式会社 半导体器件及其制造方法
US9954176B1 (en) 2016-10-06 2018-04-24 International Business Machines Corporation Dielectric treatments for carbon nanotube devices

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1053069A (enExample) * 1963-06-28
GB1175392A (en) * 1966-09-14 1969-12-23 Hitachi Ltd Method of Treating Protective Coatings for Semiconductor Devices
US3590477A (en) 1968-12-19 1971-07-06 Ibm Method for fabricating insulated-gate field effect transistors having controlled operating characeristics
NL7005296A (enExample) * 1969-04-15 1970-10-19
US3825997A (en) * 1969-10-02 1974-07-30 Sony Corp Method for making semiconductor device
DE2040180B2 (de) 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
NL7109327A (enExample) * 1970-07-10 1972-01-12
US3811974A (en) * 1971-07-19 1974-05-21 North American Rockwell Silicon nitride-silicon oxide etchant
JPS5112507B2 (enExample) 1971-10-22 1976-04-20
JPS5139835B2 (enExample) * 1971-12-27 1976-10-29
DE2218035A1 (de) * 1972-04-14 1973-10-31 Vepa Ag Verfahren und vorrichtung zum kontinuierlichen fixieren und schrumpfen von synthese-fasern
US3810795A (en) * 1972-06-30 1974-05-14 Ibm Method for making self-aligning structure for charge-coupled and bucket brigade devices
JPS5910073B2 (ja) * 1972-10-27 1984-03-06 株式会社日立製作所 シリコン・ゲ−トｍｏｓ型半導体装置の製造方法
US3898105A (en) * 1973-10-25 1975-08-05 Mostek Corp Method for making FET circuits
JPS50123274A (enExample) * 1974-03-15 1975-09-27
JPS5912495B2 (ja) 1974-10-01 1984-03-23 カブシキガイシヤ ニツポンジドウシヤブヒンソウゴウケンキユウシヨ 衝突検知装置
US3984822A (en) * 1974-12-30 1976-10-05 Intel Corporation Double polycrystalline silicon gate memory device
JPS51114079A (en) * 1975-03-31 1976-10-07 Fujitsu Ltd Construction of semiconductor memory device
JPS51118393A (en) * 1975-04-10 1976-10-18 Matsushita Electric Ind Co Ltd Semicondector unit
JPS51118392A (en) 1975-04-10 1976-10-18 Matsushita Electric Ind Co Ltd Manuforcturing process for semiconductor unit
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic
JPS51139263A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Method of selective oxidation of silicon substrate
NL7506594A (nl) * 1975-06-04 1976-12-07 Philips Nv Werkwijze voor het vervaardigen van een halfge- leiderinrichting en halfgeleiderinrichting ver- vaardigd met behulp van de werkwijze.
IT1061530B (it) * 1975-06-12 1983-04-30 Ncr Co Metodo per la formazione di connessioni elettriche in regioni selezionate di una superficie di un dispositivo semiconduttore a circuito integrato
DE2532594B2 (de) * 1975-07-21 1980-05-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Halbleiterspeicher
GB1540450A (en) 1975-10-29 1979-02-14 Intel Corp Self-aligning double polycrystalline silicon etching process
JPS6034270B2 (ja) * 1976-01-12 1985-08-07 テキサス・インスツルメンツ・インコ−ポレイテツド 半導体メモリ装置およびその製造方法
US4240092A (en) 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
US4112575A (en) * 1976-12-20 1978-09-12 Texas Instruments Incorporated Fabrication methods for the high capacity ram cell
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
FR2584786B1 (fr) * 1985-07-15 1989-10-27 Valeo Montage de butee de debrayage et butee de debrayage propre a un tel montage

Also Published As

Publication number Publication date
FR2382745B1 (enExample) 1983-06-03
DE2802048C2 (enExample) 1993-02-11
DE2802048A1 (de) 1978-07-27
JP2720911B2 (ja) 1998-03-04
JPH0918003A (ja) 1997-01-17
IT1089299B (it) 1985-06-18
JPH0362300B2 (enExample) 1991-09-25
FR2382745A1 (fr) 1978-09-29
FR2382770B1 (enExample) 1983-06-03
JPS5760852A (en) 1982-04-13
FR2382767A1 (fr) 1978-09-29
JPS62290181A (ja) 1987-12-17
FR2382768A1 (fr) 1978-09-29
FR2382767B1 (enExample) 1983-06-03
GB1595546A (en) 1981-08-12
FR2382768B1 (enExample) 1983-06-10
JPS62290152A (ja) 1987-12-17
JPS62290147A (ja) 1987-12-17
FR2382770A1 (fr) 1978-09-29
GB1595543A (en) 1981-08-12
FR2382769B1 (enExample) 1983-06-03
JPS62290180A (ja) 1987-12-17
JPH098299A (ja) 1997-01-10
GB1595545A (en) 1981-08-12
JPH0917799A (ja) 1997-01-17
JPS5394190A (en) 1978-08-17
GB1595547A (en) 1981-08-12
JPH04107840U (ja) 1992-09-17
FR2382769A1 (fr) 1978-09-29

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years

Effective date: 19980124