FR2782572B1 - Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat - Google Patents

Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat

Info

Publication number
FR2782572B1
FR2782572B1 FR9904802A FR9904802A FR2782572B1 FR 2782572 B1 FR2782572 B1 FR 2782572B1 FR 9904802 A FR9904802 A FR 9904802A FR 9904802 A FR9904802 A FR 9904802A FR 2782572 B1 FR2782572 B1 FR 2782572B1
Authority
FR
France
Prior art keywords
sur
soi
insulating
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9904802A
Other languages
English (en)
Other versions
FR2782572A1 (fr
Inventor
Atsushi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2782572A1 publication Critical patent/FR2782572A1/fr
Application granted granted Critical
Publication of FR2782572B1 publication Critical patent/FR2782572B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/914—Polysilicon containing oxygen, nitrogen, or carbon, e.g. sipos

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
FR9904802A 1998-04-17 1999-04-16 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat Expired - Lifetime FR2782572B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10108202A JPH11307747A (ja) 1998-04-17 1998-04-17 Ｓｏｉ基板およびその製造方法
FR0452015A FR2860100B1 (fr) 1998-04-17 2004-09-10 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat

Publications (2)

Publication Number Publication Date
FR2782572A1 FR2782572A1 (fr) 2000-02-25
FR2782572B1 true FR2782572B1 (fr) 2004-03-26

Family

ID=34575719

Family Applications (3)

Application Number Title Priority Date Filing Date
FR9904802A Expired - Lifetime FR2782572B1 (fr) 1998-04-17 1999-04-16 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat
FR0301536A Expired - Lifetime FR2834821B1 (fr) 1998-04-17 2003-02-10 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat
FR0452015A Active FR2860100B1 (fr) 1998-04-17 2004-09-10 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat

Family Applications After (2)

Application Number Title Priority Date Filing Date
FR0301536A Expired - Lifetime FR2834821B1 (fr) 1998-04-17 2003-02-10 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat
FR0452015A Active FR2860100B1 (fr) 1998-04-17 2004-09-10 Substrat "silicium-sur-isolant" (soi) et methode de fabrication dudit substrat

Country Status (3)

Country Link
US (2) US6211041B1 (fr)
JP (1) JPH11307747A (fr)
FR (3) FR2782572B1 (fr)

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US6346459B1 (en) * 1999-02-05 2002-02-12 Silicon Wafer Technologies, Inc. Process for lift off and transfer of semiconductor devices onto an alien substrate
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JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US6900113B2 (en) 2000-05-30 2005-05-31 Shin-Etsu Handotai Co., Ltd. Method for producing bonded wafer and bonded wafer
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
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FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
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FR2847075B1 (fr) * 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
US7176108B2 (en) * 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
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US6936497B2 (en) * 2002-12-24 2005-08-30 Intel Corporation Method of forming electronic dies wherein each die has a layer of solid diamond
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FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
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FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
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FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
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US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
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JP6634962B2 (ja) * 2016-06-15 2020-01-22 信越半導体株式会社 シリコンエピタキシャルウェーハのエピタキシャル層の評価方法及びシリコンエピタキシャルウェーハの製造方法
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Also Published As

Publication number Publication date
FR2782572A1 (fr) 2000-02-25
JPH11307747A (ja) 1999-11-05
FR2860100B1 (fr) 2006-10-13
US6211041B1 (en) 2001-04-03
US20020153563A1 (en) 2002-10-24
FR2834821A1 (fr) 2003-07-18
FR2834821B1 (fr) 2005-02-04
US6489654B2 (en) 2002-12-03
FR2860100A1 (fr) 2005-03-25

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