EP1419534A2 - Procede d'etablissement de contacts et boitiers de circuits integres - Google Patents

Procede d'etablissement de contacts et boitiers de circuits integres

Info

Publication number
EP1419534A2
EP1419534A2 EP02796172A EP02796172A EP1419534A2 EP 1419534 A2 EP1419534 A2 EP 1419534A2 EP 02796172 A EP02796172 A EP 02796172A EP 02796172 A EP02796172 A EP 02796172A EP 1419534 A2 EP1419534 A2 EP 1419534A2
Authority
EP
European Patent Office
Prior art keywords
contact
chip
wafer
cover
surface area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02796172A
Other languages
German (de)
English (en)
Inventor
Florian Bieck
Jürgen LEIB
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Schott AG
Original Assignee
Carl Zeiss AG
Schott Glaswerke AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE2001141571 external-priority patent/DE10141571B8/de
Priority claimed from DE10225373A external-priority patent/DE10225373A1/de
Application filed by Carl Zeiss AG, Schott Glaswerke AG filed Critical Carl Zeiss AG
Priority to EP10011997A priority Critical patent/EP2287916A3/fr
Publication of EP1419534A2 publication Critical patent/EP1419534A2/fr
Withdrawn legal-status Critical Current

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Classifications

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Definitions

  • the invention relates to a method for producing electrical contact connections for at least one integrated in a carrier material component according to the features of claim 1, a method for mounting at least one component in a housing according to the features of claim 29 and a device with contact connections, which at least one Component integrated in a carrier material comprises the features according to claim 64, as well as a method for producing three-dimensional integrated circuits and an integrated one
  • wafer level package method There are in which devices or integrated circuits are provided on a semiconductor chip ode ⁇ r still in the composite of a semiconductor wafer or wafer having a housing and electrical connection contacts method is known. If the assembly of the chip or the integrated circuit and the connection of the contact regions of the chip with the outwardly-guided contacts of the housing still take place in the wafer composite, then such an assembly method is generally referred to as "wafer level package method".
  • the mentioned method is characterized in that after applying a glass cover on. the optically active front side of a wafer along the underside of the wafer trenches are generated, which divide the wafer into individual chip areas.
  • the connection pads located on the active side of the wafer are each shared on the transition area between two chips and thus exposed in the trenches.
  • Glass pane glued which is cut in a corresponding manner so that the trenches in the wafer and the terminal contact points are in turn freely accessible. This is followed by a deposition of contact paths in the trenches generated, thereby contacting the
  • the object of the present invention is to avoid the abovementioned disadvantages of the prior art, in order to thus provide a less expensive and simpler method for producing electrical contact connections in the packaging, in particular of optical chips.
  • Characteristics claimed in claim 31 and in the independent claim 66 defines a device which can be produced in particular according to one of the inventive method. Advantageous developments can be found in particular in the respectively associated subclaims.
  • a method for producing electrical contact connections for at least one component integrated in a carrier material, wherein the carrier material has a first surface area and wherein at least one contact terminal is arranged at least partially in the first surface area for each component, in particular by applying a cover on the first surface area and generating at least one contact channel extending transversely to the first surface area in the substrate, or in a direction substantially perpendicular thereto, wherein at least one pad in a second surface area to be provided over the respective contact channels at least one electrical contact connection is made from the contact point to at least one of the terminal contacts.
  • a contact point on the side of the carrier material facing away from the contact surface and thus on the active surface can be produced such that a contact point in electrical connection with the terminal contact is produced.
  • the carrier material in which the components are integrated is subdivided into chip regions to be defined, based on the arrangement of the components.
  • the for the Contact connection provided contact channels can be introduced according to the invention in various ways in the carrier material.
  • the invention also provides for introducing the contact channels into the carrier material in such a way that, in particular, they connect substantially directly to the connection contacts, starting from the second surface area.
  • the latter variant offers the particular advantage that it is not necessary to relocate the connection contacts on the first surface area.
  • Relocation in this context means that a contact track is produced on the first surface area, which establishes an electrical connection between the terminal contact and the contact channel.
  • An introduction of the contact channel next to the terminal contact may be particularly advantageous if, for example, below the terminal contact T'eile of active areas of the component integrated in the substrate are located.
  • the contact channels or at least parts thereof are introduced there into the carrier material, where in a later method step, the carrier material is cut into different chip areas. Since it is possible according to the invention to produce more than one electrical contact connection by means of a contact channel, it is thus possible in a simple manner to establish a contact connection to a plurality of connection contacts on, for example, different chip areas or for different components via the individual contact channels. Highly advantageous according to the invention, the possibility to produce the contact channels in different ways.
  • the contact channel is provided by doping the carrier material. In this case, preferably chemical elements of the third and fifth main group of the periodic table are used. The doping method used is preferably the ion implantation or thermal de-bonding of the elements into the carrier material to produce the contact channels.
  • the production of the contact channels comprises the provision of hole openings.
  • holes offer the advantage that not only a contact connection can be laid through them, but, of course, depending on the size of the hole opening, a plurality of contact paths can be laid in the opening.
  • the hole openings or the contact channels laterally relative to the substrate in particular electrically isolated.
  • the channels for conducting the contacts through the semiconductor material or carrier material may preferably be produced either by means of a dry etching process and / or a wet etching process.
  • the dry etching process according to the invention regularly comprises photolithographic patterning of the surface to be processed and anisotropic dry etching.
  • the etching by means of KOH caustic comes into consideration.
  • Last process offers cost advantages in particular.
  • Contact channels which are to produce a contacting penetration from one surface area to the other surface area of the carrier material or of the wafer, are arranged at different locations in the carrier material or in the chip or in the wafer. According to the invention, it may be necessary to match that the connection contacts located in the surface area are relocated to the respectively assigned contact channels in order to produce the electrical contact connection or contact connections.
  • the relocation can be done by conventional photolithographic
  • Structuring and corresponding etching and the deposition of electrically conductive material take place.
  • a variety of known deposition or coating methods can be used according to the invention. These are z.
  • contact channels according to the invention are produced, for example, by hole openings, then these can be combined with the mentioned methods with electrically conductive materials such.
  • electrically conductive materials such as aluminum and / or copper and / or nickel and / or comparable metals can be filled in order to produce in this way a contact connection from the first surface area to the second surface area.
  • connection contact for a printed circuit board is produced in a simple manner, for example.
  • a relocation of the created contact point can be provided with advantage also on the second surface area.
  • the inventive method provides the ability to mutually isolate the contacts the contact channel or provided with tracks hole openings in the other to fill with insulating material. Later, when the hole openings filled in this way are divided into individual chips as part of the dismantling of the wafer, lateral isolation of the singulated chips can already be ensured in this way.
  • the cover is preferably provided in the form of a glass or a similar plastic.
  • a glass or plastic itself in particular when cover optically active components Sind._
  • the connection between the cover and the first and / or second surface region is carried out according to an embodiment of 'the invention by means of an adhesion promoter.
  • special mechanical or optical properties can also be achieved, for example, with a cover which comprises a glass-plastic composite material or layer material.
  • Epoxy resins and / or waxes and / or sol gels can preferably be used as adhesion promoters.
  • the use of wax in particular has the advantage that the compound thus created can be released again without destroying the carrier material.
  • the preparation of a connection between the cover of preferably glass and the support material based on a sol gel proves to be particularly advantageous in that the gel has a comparatively high transparency and moreover enters into a very temperature-resistant compound with glass in particular. Since the sol gel itself is vitreous, so to speak glass itself, it also has particularly good matching or transition properties, especially with regard to glass.
  • Another related advantageous embodiment of the invention is also to replace the bonding agent for bonding the cover to the substrate by a so-called bonding.
  • a so-called bonding preferably an anodic bond is considered.
  • the bonding requires a substantially planar surface or a planar surface region of the support material. Therefore, it is advantageous, if the topographic differences on the substrate or wafer are too large, first an oxide layer on the wafer surface or the
  • the carrier material To deposit surface areas of the carrier material. Methods which can be used for this purpose are, for example, the “LTO (Low Temperature Oxide)” and the “TEOS (Tetra-ethyl-ortho-silicate) method.” Furthermore, as part of the bonding of the cover to the carrier material, the deposited Oxidized oxide layer by means of a chemical mechanical polishing process such that the micro and macroplanarity for the bonding is provided.
  • LTO Low Temperature Oxide
  • TEOS Tetra-ethyl-ortho-silicate
  • the order of the steps "applying a cover” and “producing at least one contact channel” varies according to the invention.
  • the cover is first applied to the first surface area of the carrier material before the contact channels are introduced into the carrier material.
  • the active components are located in the first surface area.
  • the application of the cover has the advantage that the components located in the carrier material are protected u ⁇ d the arrangement additionally gains in stability.
  • the carrier material or the wafer or the semiconductor wafer can then be thinned on the back, for example mechanically by a Abschleifrind without losing its mechanical stability, which is ensured by the cover.
  • the via ie the production of at least one contact channel in the thinned carrier material, then takes place according to one of the possibilities described above on the basis of the generation of doping channels or with the aid of openings provided with conductive material.
  • connection contacts lying on the active upper side can be through-contacted directly, starting from the provided second surface area, via the respective contact channels, as it were from behind.
  • a further embodiment variant of the production process according to the invention of contact channels or contact connections is that the blind channels are produced in the carrier material before the cover is applied and the carrier material or wafer is thinned out from the front or from the first surface area.
  • the term sack channels was chosen because these channels usually do not reach through to the second surface area.
  • the sack channels are formed in the form of blind hole openings, ie in the form of openings whose depth is initially lower than the thickness of the carrier material, then an insulator for electrical insulation of the hole is applied to the carrier material and laid or deposited on these contact paths on the Sacklochwandungen in general and / or thereafter filling the blind holes with a conductive material.
  • a cover is applied to the first surface area of the wafer or substrate. Due to the particular stabilizing effect of the cover with respect to the carrier material, it is now possible to thin out the carrier material starting from the passive side of the carrier material with the aid of a preferably mechanical grinding process. The thinning is carried out until at least in the region of the blind hole, the printed conductors or conductive materials introduced therein are exposed, so that a through-contacting of the carrier material or wafer or chip or substrate is formed.
  • a corresponding procedure is also followed when the contact channels are generated on the basis of the carrier material initially not penetrating doping channels.
  • a method for mounting at least one component in a housing In this method, first at least one semiconductor component in a carrier material, which has a first. Surface area, which comprises a second surface area opposite, provided or provided, wherein at least one terminal contact is at least partially disposed in the first surface area for each integrated circuit. Furthermore, using the above-presented method, a carrier material provided with a first cover on the first surface area is produced with at least one contact point in the second surface area, and then a second cover is applied on the second surface area.
  • the second cover With the help of the second cover, it is advantageously possible to protect the semiconductor device against damage from the outside. Furthermore, the second cover justifies the possibility that, if the first cover on the first surface area with z. B. was applied to a wax, which can be removed again for further processing steps, without causing the possibly thinned wafer or chip would lose stability.
  • Inserted hole openings where the laid on the second surface area terminal contacts of the semiconductor device are located. It is of course free to bring the cover penetrating hole openings before the actual application in the cover layer.
  • conductive material such as aluminum, copper or nickel are filled in order in this way a compound of the laid connection contacts outside.
  • the carrier material or the semiconductor wafer comprises a plurality of components or integrated circuits relates to the formation of isolation trenches between the components or integrated circuits. These trenches are preferably used for electrical decoupling or isolation of the individual components on the different chip areas. For this purpose, the trenches created can also be filled with an insulating material.
  • Insulating material is z.
  • the separating trenches are arranged on the wafer or on the semiconductor wafer in such a way that the wafers are divided into substantially substantially equal sizes via a substantially symmetrical division of the separating trenches
  • Chip areas is decomposed. Most advantageously, in this way, the components lying on the chips can also be laterally sealed or insulated from the outside.
  • both the laying of the connection contacts and the assembly of the components in a housing according to the invention take place in the wafer composite. It is also within the scope of the invention to provide a method for producing integrated circuits, which is also particularly suitable for producing multilayer integrated circuits. The method is suitable, in particular, for producing multilayer integrated circuits or for mounting inventively produced circuits on suitable substrates.
  • Semiconductor integrated circuits are often used for miniaturization of electronic components, which are applied alone or together with other circuit components or other circuits on their own semiconductor substrates or semiconductor wafers.
  • Such a semiconductor substrate with an electronic component or preferably at least one electronic component is often used for miniaturization of electronic components, which are applied alone or together with other circuit components or other circuits on their own semiconductor substrates or semiconductor wafers.
  • Circuit component is to be referred to in the following simplified as a chip.
  • MOEMS micro-optoelectromechanical systems
  • CMOS technology is mostly used for logic and processor applications.
  • CMOS chips make it difficult to realize optical or sensory components.
  • a highly integrated memory circuit can advantageously be integrated into the image recording unit.
  • the CCD chip can be combined with a processor chip for data compression, so that in the other electronics of the device subsequently only compressed data must be processed.
  • This side of the chip is then covered with an insulating protective layer, which is so thick that the solder bumps are completely covered.
  • the protective layer is ground and polished in a further step until the contacts are partially exposed.
  • the thus treated chip is then connected to the substrate by melting the electrodes and the protective film, the electrodes being associated
  • This method can be used for the production of stacked components, which are hereinafter also referred to as electronic components due to their autonomous handling, with optoelectronic elements in general, because the optically, or sensory active side of the pad or connected to the optical component Element would be covered.
  • the invention accordingly provides a method for
  • Producing integrated circuits in which a wafer is used, which has a substrate, at least one terminal contact and on a first side of an active layer comprising the circuits of a chip.
  • the method comprises the steps:
  • Circuits are further developed with at least two chips, each having at least one terminal contact and on a first side of the circuits of the chip comprehensive active layer.
  • the method provides for fixing a cover on one side of a first of the at least two chips.
  • a conductive channel is introduced into the substrate, which extends in a direction substantially perpendicular to the surface of the chip, or to the first side of the chip.
  • a contact surface is produced, which is electrically connected to the conductive channel.
  • at least one terminal of the circuits of the first chip on the first side is connected to the conductive channel.
  • the first and at least one further chip are fastened to one another such that an electrical contact is produced between the electrically conductive channel of the first chip and at least one corresponding terminal surface of the other chip.
  • the at least one conductive channel can be generated in various ways. According to one embodiment of the method, the channel is created by inserting a hole, which is then filled with a conductive material, such as a metal or a conductive epoxy.
  • a conductive material such as a metal or a conductive epoxy.
  • the channel can be created by inserting a suitable doping.
  • the doping can be carried out, for example, with ion implantation or thermal diffusion.
  • the first chip is thinned on the second side, which is opposite to the first, the active layer having side.
  • the hole is made with a depth that is initially less than the thickness of the substrate, a blind hole is formed.
  • the depth of penetration of the dopant may not be sufficient to produce a conductive channel extending from one side to the other side of the substrate.
  • the thickness of the substrate is at least in the region of the hole o_der the doping less than the depth of the hole, or the thinning by the step of thinning
  • the holes are preferably produced by means of etching and thus represent etching pits in the substrate.
  • the inventive method makes it possible to connect a chip with a pad, in particular another chip so that the pad faces the back of the chip and in addition electrical connections of the top or active side of the chip are made with the pad.
  • the chip is provided with conductive channels extending from the top to the bottom.
  • the channels are provided with a conductive layer or filled with a conductor to make a via.
  • a surface area of the chip may be doped so that a conductive region forms through the doping, which can extend to the opposite side and thus forms a conductive channel.
  • the guided through the chip by means of the conductive channels contacts can then be provided with solder bumps, with which the chip is connected to the pad.
  • the connection of the chips can be carried out, for example, in a manner similar to that described in US Pat. No. 6,171,887.
  • the contacts may of course be applied to the other chip as well or both.
  • the channels which serve to conduct the contacts through the semiconductor material can be produced inter alia by means of a dry etching process.
  • a dry etching process Particularly suitable for this purpose is an anisotropic dry etching process such as, for example, the SF 6 -radical-based "ASE process ⁇ .
  • An inexpensive alternative here is the anisotropic etching with KOH liquor, which in the case of Si wafers in (100)
  • Orientation offers Of course, combinations of the above-mentioned methods for generating the channels may also be used. Furthermore, these methods can also be used to create isolation trenches, wherein the isolation trenches can be produced, for example, in one step can be etched together with the channels. However, it is also possible, inter alia, to use for the etching of the separating trenches and the etching of channels in each case another of the above-mentioned methods or another combination of these methods.
  • the device to be connected to the optical or sensory chip requires vias for connection to the board or to another chip.
  • This chip is therefore prepared similarly to the overhead optical or sensory chip, the device having two sets of pads.
  • the blocks are preferably still in the wafer assembly, that is, they are not yet separated from the wafer during production.
  • the wafer is glued on the optical side with a transparent cover, such as a thin glass sheet.
  • Blocks on the wafer are thereby protected and the arrangement gains additional stability.
  • a suitable epoxy resin can be used.
  • the wafer can then be thinned mechanically on the back by a grinding process, the mechanical stability is further ensured by the transparent cover.
  • the plated-through holes can be produced in two different ways.
  • the upper side of the optical chip is patterned photolithographically and the etch pits brought in.
  • the conductive channels are in this variant next to the contact surfaces or bond pads for connecting the chip.
  • the etch pits are then filled with a conductor and a conductor track applied from the etch pit to the bondpad.
  • the transparent cover may be applied and the wafer is then thinned out on the backside until the conductive fillings of the etch pits protrude on the surface of the backside.
  • the cover is applied in advance and the wafer is thinned out.
  • the photolithographic patterning and the etching in this case take place from the underside of the chip, wherein the etch pits are located below the topside bond pads and etched until the bond pads are exposed.
  • the non-optical chips are prepared, which method can also be done here in the wafer association.
  • the non-optical chips on which the optical chips are applied initially have two sets of contact pads or bond pads which serve for through-connection or for connecting the optical chip or an overlying chip.
  • the afer with the non-optical chips is also thinned, but without endangering the stability.
  • the thinned wafer is then photolithographically structured and etched through at the locations provided for the via. These patterning and etching operations may be performed from the top, active side and bottom, as in the case of the optical chips.
  • the channels formed by the etch pits through the wafer are then metallized or filled with a conductor.
  • the Contact surfaces with tracks connected to the filled channels.
  • the contact surfaces are provided on both sides with solder bumps. It may be possible to dispense with the application of these contacts, which are provided for the connection of the optical chip or overlying chips, if such fusible contacts are already located on the associated contacts of the overlying chip.
  • the chips prepared in this way can then be connected together. If the chips are arranged on the wafers in the same way so that the corresponding contacts come to lie one above the other when the wafers are stacked on top of each other, the bonding of the chips in the wafer assembly can be carried out. Otherwise, the wafer with the smaller chips is sawed by means of a dicing saw and the chips are then placed on the other wafer. By means of reflowing or reflowing the solder of the solder bumps, the two wafers or chips are then connected to the wafer to produce contacts between the chips. In order to connect the wafer or chips to one another, it is preferred to use a refractory solder which has a higher melting temperature than the solder used to connect to the board. This prevents that the connections of the chips of the chip stack with each other when connecting to the board solve again. For the connection of the chips with each other, for example, pure tin can be used. The chips are separated in a final step with a dicing saw.
  • the chips on the wafers can be wrapped with various wafer-level packaging processes after the transparent cover has been applied.
  • the method according to the invention also makes it possible to connect more than two layers of components or chips, wherein the correspondingly prepared parts are connected to one another either simultaneously or successively.
  • the elements of the multilayer integrated semiconductor device successively fastened to each other, so it allows the last attached wafer or chip through the composite.
  • the elements additionally lent mechanical stability that it can be thinned comparatively further.
  • This embodiment is therefore based on a successive mounting together with subsequent thinning of the wafer or chips. This has the consequence that the holes or etching pits in the chips must be etched through a comparatively thinner substrate and thereby remain smaller in diameter.
  • the top chip of the stack produced by the process need not be an optical chip. Rather, any semiconductor devices can be combined with one another to form compact three-dimensional stacks with the invention.
  • the method is particularly suitable, for example, for stacking memory chips which can be interconnected without an interlayer insulating layer.
  • integrated circuits on different substrates, such as Ge, Si and GaAs can advantageously be combined to save space.
  • a variety of sensory chips can be combined with other components.
  • the sensory chips may include, for example, radiation pressure, temperature or humidity sensors. Also chemically sensitive sensors can be used which are based on specific gases or Address liquid components.
  • a transparent cover can also be structured in an advantageous manner.
  • optical elements such as prisms, gratings or optical filters can be integrated into the cover.
  • the chip can also be fixed by means of a removable wax on a base, which during the Manufacturing process, in particular during the thinning gives additional strength.
  • the cover can also be fixed, for example, by means of an epoxy resin during the production process, which is detachable again under the action of UV light.
  • Circuit arrangement which comprises at least two chips arranged one above the other, each having a substrate, at least one terminal contact and on one side an active layer comprising the circuits of the chip.
  • At least one of the chips of the circuit arrangement advantageously has a conductive channel, wherein electrical contacts between at least one terminal of the circuits of the chip having the channel and the conductive channel on the one hand and a pad of the other chip with the conductive material on the other hand.
  • the finished composite multilayer semiconductor integrated device can additionally be provided with a protective housing.
  • a multi-layered Integrated circuit arrangement produced by the method according to the invention and provided with an advantageous protective housing in the course of manufacture constitutes a packaged multipackage as claimed in claim 79.
  • a packaged multipackage thus likewise comprises at least two stacked chips arranged on one side respectively have at least one terminal contact and an active layer comprising the circuits of the chip.
  • the chips thus arranged are advantageously at least partially enclosed by a housing.
  • at least one of the chips of the one conductive channel wherein also an electrical contact between at least one terminal of the circuits of the chip having the channel and the conductive channel on the one hand and a pad of another chip with the conductive channel on the other hand.
  • a device which preferably includes a sensory or optical or a corresponding outwardly active component, wherein the device via two covers on the first and second surfaces and a lateral insulation outwardly insulated or is protected.
  • FIGs. a representation corresponding to the Figs 1 to 2A of 2C possible further steps in the
  • Fig. 1. Figs. the method steps according to another 3A to 3D embodiment of the method according to the invention. Figs. a variant of the method shown with reference to the figures 3A to 3D 4A to 4D with a redistribution of
  • FIG. 1 Another embodiment of the invention at 6A and 6B were introduced between the chip areas on the wafer from the passive side of separation trenches.
  • Figs. an embodiment according to the invention in the 7A and 7B along the parting lines between the chips on the
  • Chip with an underlying chip to one
  • Chip stack can be joined together, Figs. with reference to schematic cross-sectional views 10A to a further embodiment of the 10E process according to the invention,
  • Fig. 12 is a cross-sectional view of another embodiment.
  • FIGS. 1A to IE show the method steps of a first variant of the method according to the invention for the production of electrical contact connections on the basis of different cross-sectional views of a wafer or semiconductor wafer 10.
  • This is preferably a sensory chip and in this case, for example, an optical or pressure-sensitive or moisture-sensitive etc. act in which is of particular importance that after 'contacting or attaching or contact bonding of the chip on eg a board or other equipment or
  • FIGS. 1A to 1C show, by means of cross-sectional views, also method steps which are suitable for preparing a chip for joining to a three-dimensional chip stack.
  • the optical chip or sensory chip according to FIG. 1A is arranged in the wafer composite 10 and, corresponding to the semiconductor wafer 10, consists of a substrate 1 to whose
  • Top 14 is an optically active layer 11, such as the sensor layer of a CCD chip.
  • the upper side 14 of the chip is additionally covered by a passivation layer 13.
  • On the surface are alsomaschinetechniksflachen or bonding pads 12, which are used for connection of the chip and are connected via conductor tracks with the optically sensitive layer 11.
  • openings 16 are first made or introduced into the passivation layer at the locations provided for the plated-through holes, and the substrate is uncovered. This step can be carried out, for example, by photolithographic patterning and subsequent ion beam etching.
  • etch holes or blind holes 17 are etched into the substrate, wherein the
  • Passivation layer 13 protects the substrate outside the openings 16 before etching.
  • Anisotropic etching of an Si (100) substrate with KQR_ is suitable for the production of the etching pits, etching pits having an opening angle of approximately 70 °, the diameter or cross section of which on the active surface being one of the etching depth and / or the opening angle depends.
  • Figure IC shows a cross-sectional view of the chip after these manufacturing steps.
  • the etch pits 17, as well as areas of the upper side 14 between the etch pits are coated with a metal.
  • a metal layer 18 is formed, which is located on the walls of the etch pits and on the ladder-shaped areas between the etch pits, the layer at least partially covering the bondpads in order to ensure a secure connection Establish contact.
  • a contacting metal for example, aluminum, copper or nickel is suitable.
  • the metal coated etch pits are next filled with a metal so that the pits are filled with a solid conductive structure 19.
  • Figure IC shows a cross-sectional view of the chip after these manufacturing steps.
  • the etch pits 17, as well as areas of the upper side 14 between the etch pits are coated with a metal.
  • a metal layer 18 is formed, which is located on the walls of the etch pits and on conductor-shaped areas between the etch pits, the layer at least partially covering the bond pads in order to produce a secure contact.
  • a contacting metal for example, aluminum, copper or nickel is suitable.
  • the metal coated etch pits are next filled with a metal so that the pits are filled with a solid conductive structure 19.
  • the pit may first be filled with a conductive material and then a trace may be laid from pad 25 to pad 19 to make electrical contact.
  • the upper side 14 of the chip 1 is provided with an optically transparent cover 20 for the purpose of protecting the optically sensitive layer 11.
  • Fig. 1D Manufacturing phase is shown in Fig. 1D.
  • the cover also has the function of mechanically stabilizing the entire structure, which is the case for the subsequent method steps, in particular for the one to be described later Thinning the wafer, starting from the passive side, is important.
  • the cover 20 is preferably adhered to the chip by means of an epoxy resin layer 21.
  • a cover for example, a glass or comparable transparent plastic is suitable.
  • the bottom or inactive side 22 of the chip is ground until the conductive fillings 19 of the etch pits 17 are reached, thereby forming contact pads 23 on the bottom 22 of the chip.
  • the contact point may, for example, have a width of approximately 50 ⁇ m according to one of many possible embodiments.
  • the wafer has a total thickness of, for example, about 500 .mu.m
  • the blind hole has a penetration of slightly more than 200 .mu.m, so that after thinning of the substrate, the blind hole tip is exposed to a width of 50 .mu.m.
  • This manufacturing state is depicted in FIG. IE.
  • the wafer is now in a shape such that the bond pads are on the passive side of the wafer. It can now be processed as a non-sensory chip, e.g. with all known Wafer Level Packaging (WLP) processes.
  • WLP Wafer Level Packaging
  • FIGS. 2A to 2E show further possible method steps which can follow the method step according to FIG. IE.
  • FIGS. 2A to 2C also show, in particular with reference to cross-sectional views through a chip, various embodiments of the chip shown in FIG. IE for further possible processing steps which are suitable as preparation for joining chips produced according to the invention into a chip stack.
  • solder bumps for example, which are connected to the contact surfaces.
  • the solder bumps 24 are applied directly to the contact surfaces 22. It may also be possible to redistribute or redistribute the connection points on the underside of the chip. This may be necessary, for example, if the other
  • FIG. 2B One way to apply redistributed contacts to the passive side of the chip is shown in FIG. 2B.
  • bonding pads 25 are first attached to the desired positions on the back side of the chip. Subsequently, conductor tracks are applied from the bond pads 25 to the contact surfaces 23 formed by the abrading and / or etching of the rear side at the fillings 19 and solder bumps 24 are applied to the bond pads 25.
  • a further cover 27 is applied on the underside 22 of the chip.
  • Such a sandwiched "sandwiched" chip between two covers 20 and 27 can be seen from Fig. 2C. Since the coefficients of thermal expansion of the cover glass 20 and, for example, semiconductor material of the chip or substrate 1 may be different, it may occur when heated or
  • the bottom material 27 (BCB, plastic, glass, etc.) must be mechanically fitted to the top material and, if possible, so as to compensate each other for the rigidity of the materials consisting of thickness, modulus of elasticity, and coefficient of thermal expansion. It is by no means necessary that the upper material 20 must be identical to the lower 27.
  • the substrates of the chips to be stacked different thermal expansion coefficients or in operation have different temperatures, also offers the use of an intermediate layer between the chips, which can reduce by their flexibility, the resulting between the substrates temperature stresses .
  • the embodiment shown in Fig. 2C may also be provided for stacking chips with such a flexible intermediate layer.
  • first the underside or passive side 22 of the chip is provided with an intermediate layer 27.
  • the layer 25 has channels 28, which fit in their arrangement in the cover with the contact surfaces 23.
  • the channels can be filled with a conductor 29, similar to the etching pits 17.
  • a suitable method consists, for example, in a galvanic deposition of Cu or Ni.
  • a conductive epoxy can be pressed into the etching pits. The contacting with solder bumps 24 can then proceed in the same way as in the previous exemplary embodiment.
  • FIGS. 3A to 3E likewise show, with reference to cross-sectional views of a chip area of a semiconductor wafer, the method steps according to a further embodiment of the method according to the invention.
  • the method steps shown in FIGS. 3A to 3E according to this further exemplary embodiment of the invention are likewise suitable for preparing the assembly of a chip into a multilayer integrated circuit arrangement.
  • the top 14 of the as shown in FIG. 1A prepared chips 1 first glued over an adhesive layer 21 with a thin transparent cover 20.
  • This intermediate stage of the process is shown in FIG. 3A.
  • the thus prepared chip or wafer can then as shown in FIG. 3B, are thinned on its underside 22 safely, since the structure has gained sufficient stability by the composite with the cover.
  • the thickness of the wafer should, as already mentioned, be as small as possible after the etching and / or grinding.
  • etching pits 30 are then inserted into the chip, wherein, in contrast to the preceding exemplary embodiment, etches are now etched starting from the underside 22 until the etching pits strike the bond pad 12 located on the upper side 14 of the chip.
  • the metal layer of the bond pads 12 acts as an etch stop.
  • the etching process or the deep etching is preferably carried out in connection with a photolithographic patterning and an anisotropic dry etching method, e.g. the so-called "ASE process" with SF6.
  • ASE process anisotropic dry etching method
  • the holes thus created taper inward or widen outward.
  • a blind hole produced in this way rounds at the end of the blind hole or here at the bond pads.
  • the edges or walls of the etching pits or hole openings 30 are then isolated via a conformal plasma oxide deposition relative to the substrate 1.
  • the insulating layer is marked 32.
  • Such insulation 32 ' is basically optional. However, it is often necessary if the substrate is highly doped to avoid short circuits. In this respect, the method based on SiH4-based LTO (Low Temperature Oxide) method or based on TEOS oxides (TEOS, tetra-ethylene-ortho-silicate) method come into consideration.
  • the plasma oxide deposition is typically followed by a back etch step to, among other things, expose the backside of the bond pads 12. Following this, as can be seen from FIG. 3D, the etching pits or hole openings 30 are filled with a conductive material.
  • the fillings 31 can in turn be carried out by electrodeposition of metal in the etching pit or by filling the openings with a conductive adhesive (conductive epoxy) by means of the screen printing / squeegee technique
  • FIG. 2A shows such a variant of the method illustrated with reference to FIGS. 3A to 3D, with a redistribution of the terminals analogous to the embodiment shown in FIG.
  • the regions 31 in the figures may also represent conductive doped regions which also make a via through the substrate.
  • FIGS. 5A to 5C show possible further method steps with regard to a complete housing of the chips 1a and 1b in the wafer assembly 1.
  • the method steps already described above for through-connection and production of the contact surfaces 23 are made.
  • will be additional generates trenches along the parting lines on the wafer of adjacent chips by suitable etching processes.
  • Such a generation of trenches between the chips affords the possibility of lateral sealing of the chips with, for example, epoxy resin, so that there is no longer any bare silicon.
  • the active front and the back of the passive wafer 1 or the chips la and lb are coated as usual with covers.
  • a photostructurable layer 27 eg BCB or Benzocyclobuten
  • FIGS. 6A and 6B For this purpose, reference is also made by way of example to FIGS. 6A and 6B.
  • the trenches 35 corresponding to the hole openings were inserted into the substrate 1 from the back side of the wafer 1 (FIG. 6A). If, as discussed above and as shown in FIG. 6B, a BCB layer is applied to the rear side, the trenches 35 are also filled with BCB in insulating form and a lateral seal is effected. At the trenches 35 is later the
  • the trenches 35 can also be produced by an anisotropic dry etching process, such as by means of an ASE process or by anisotropic etching with KOH alkali.
  • the etching of the etch pits as well as the trenches 35 can also be performed by a combination of different etching processes.
  • an etch pit or a separation trench can be produced in a first step by means of wet etching and then further by means of anisotropic dry etching.
  • both the same etching method as well as different etching methods or combinations of the etching processes for the production of trenches and etching pits can be used.
  • a possible Embodiment provides, for example, wet-chemical pre-etching of the separation trenches and then subsequent co-etching of surface areas for trenches and conductive channels by anisotropic dry etching.
  • the shape, such as the wall steepness, as well as the size and depth of the etched structures can thus be advantageously controlled.
  • FIGS. 7A and 7B show a further embodiment of a through-connection according to the invention. Fig. 7B shows the
  • the via channels 17 and 19 are here along the chip separation lines 36 on the wafer. In this way it is easily possible via an etching pit 17 to contact two or more bond pads 12a and 12b of adjacent chips 1a and 1b by suitable redistribution of the contact points to the through-connection point 19. For this purpose, after an electrical insulation of the walls of the blind hole opening were laid in these contact tracks 18. However, in contrast to the process according to FIGS. 1A to 1 IE, the blind hole opening was not additionally filled with a conductive material, but with an insulating material 37. This has the positive effect that after the wafer has been severed along the dividing line or along the via points isolated chips are laterally insulated from the outside.
  • the underlying building blocks are prepared. Possible embodiments are shown in the cross-sectional views of FIGS. 8A to 8C.
  • the chips located under the top chip in the chip stack require two sets or types of bond pads, one set serving to make contact with the overlying chip and the other set to connect to the underlying chip or die Case that the chip is the bottom of the stack is to make the connection with the board or a designated pad.
  • the chip is thinned out on the passive side as far as the stability requirements during the
  • FIG. 8A shows a first possible embodiment of such a chip 2, which may be, for example, a memory chip.
  • the chip 2 like the chip 1 described above, has an active layer 11 below a passivation layer 13, in which the components of the integrated circuit are located.
  • solder bumps 24 are applied, which are later used for connection to the overlying chip, such as the top chip 1.
  • Etched pits 30, which extend up to the bond pads 42 of the second set of contact surfaces, are etched into the underside 22 according to the embodiment of FIG. 8A.
  • the channels formed thereby are also filled as in the top chip 1 with a conductor 31.
  • Soldering beads 33 are again melted onto the contact surfaces formed on the underside 22 of the chip by filling them in order to contact the next level of the chip stack.
  • the solder used for the solder bumps 33 may advantageously have a lower melting point, as the material used for the other solder bumps 24.
  • the assembled chip stack can be on a board or other pad by melting the solder bumps 33rd fasten, without the other solder bumps 24 melt.
  • FIG. 8B shows another embodiment in which, analogously to the arrangement shown in FIG. 3E, the connection contacts consisting of bond pads 25 were redistributed with solder bumps 33 and are connected to conductor tracks 26 with the contact surfaces 34 of the padding 31.
  • FIG. 8C shows a further embodiment of the chip 2 in which, similar to FIG. 2C, a bottom cover 27 has been applied, which can act as a protective packaging and / or flexible intermediate layer
  • the chip is as in the previous example and as in Fig. 2C with redistributed contacts, consisting of bond pads 25 with
  • the channels 28 are also filled with a conductive filling 29 here.
  • a conductive filling 29 it may be expedient to redistribute the contacts in such a way that the contacts lying on the underside and top side of the chips match one another in their lateral positions.
  • multiple chips 2 can be combined with each other arbitrarily with regard to the order and number in a chip stack. This can be advantageous, for example, if such a chip stack comprises a plurality of memory modules.
  • several different variants, which differ only in the number of stacked memory modules can be manufactured from the same individual components without unnecessarily high outlay.
  • FIGS. 9A to 9C show, by means of cross sections, the steps of an embodiment, such as the uppermost chip an underlying chip can be assembled into a stack.
  • Adhesive layer 21 is connected to a cover 20 and has on the underside carried contacts solder bumps 24, the block is coated on its underside 22 with an adhesive layer 45, as shown in Fig. 9A.
  • a thermoplastic material can be used for this layer. The layer thickness is chosen so that the solder bumps 24 are completely covered.
  • the layer 45 is abraded until the solder bumps 24 emerge and are ground flat together with the layer, so that, as shown in Fig. 9B, flat contact surfaces 36 arise. Solder beads 37 are placed on these surfaces again.
  • FIG. 9C shows the optical chip 1 connected to another chip 2.
  • the solder of the solder bumps on the bond pads 25 of the two chips is melted by heating, and the solder bumps on the contact surfaces of the two chips 1, 2 merge to form a solder joint 39 Heating also softens the thermoplastic
  • the surface tension of the molten solder also causes a self-adjusting effect when the chips are put on top of each other. Due to the surface tension, the chips are pulled in one direction so that the lateral spacing of the contact surfaces 25 between the chips connected to each other via the solder becomes minimal.
  • a further exemplary embodiment of the method according to the invention is explained below with reference to the schematic cross sections of FIGS. 10A to 10E. This embodiment is based on a successive mounting with subsequent thinning of the wafers or chips, wherein the combination of the already assembled elements provides additional stability to the last-added package or wafer so that it can be further thinned out.
  • first a cover 20 is again fixed on the first or uppermost chip 1.
  • the substrate 100 of the chip 1 is then thinned out (FIG. 6B) and vias formed according to the methods described with respect to FIGS. 3A to 3E (not shown).
  • the next chip 2 is placed and fastened by connecting the vias on the first chip 1 with associated terminals on the other chip 2.
  • the patched chip 2 has at this time still no etch pits, holes or doped regions for the via. Since the patch wafer or chip but now firmly connected to the first chip i has the patch chip 2 by the composite with the first chip 1 and the cover 20 has a mechanically stable surface and can safely as far as the first chip 1 de-s stack be thinned out.
  • Chip stack is formed, as shown schematically in Fig. 10E with three chips 1, 2 and 3 stacked on each other.
  • the chips can be connected to one another both directly and via insulating and / or flexible intermediate layers.
  • the bonding or bonding together, or connecting the chips to a stack in the wafer bond can be accomplished.
  • the prerequisite for this is that the chips are arranged laterally on different wafers in the same way, so that the chips of a stack come to rest on one another when the wafers are placed on top of each other.
  • the stacked chips in the wafer assembly can then be separated with a dicing saw.
  • FIGS. 11A to 11C show embodiments of chip stacks 6 with three layers produced as described above.
  • FIG. 11A shows an embodiment of a chip stack 6 in which the uppermost chip 1 is not an optical component but comprises another integrated circuit, the side with the active layer 11 facing the underlying component 2.
  • via of the top chip is not necessary.
  • the underlying chips 2 and 3 have vias, which were prepared according to the inventive method.
  • the conductive fillings 31 of the plated-through holes of the chips 2 and 3 are over Soldered connections 39 are connected to corresponding bonding pads 25 of the respective overlying chip 1 or 2.
  • the chip stack 6 can thereby continue to be used as in the so-called "flip-chip” technique and be connected to contact surfaces of the intended substrate, such as a circuit board, by melting the solder bumps 24.
  • the resulting multilayer integrated module or chip stack 6 can be sealed with an epoxy coating 40.
  • FIG. 11B shows a possible embodiment of a chip stack 6 with an optical chip as topmost element.
  • the optical chip 1 is provided according to the method steps shown in FIGS. 1A to IE, in which the through-etching of the substrate takes place from the top side or the active side, and then onto the wafer via an optical epoxy resin layer 21 a transparent cover 20 is applied.
  • the chip is then bonded together with the lower chips 2 and 3 prepared as described with reference to Figs. 40A to 40C.
  • the bonding can be carried out as described with reference to FIGS. 9A to 9D.
  • the underside of the chip stack is also provided with a cover which serve as a flexible intermediate or leveling layer between the bottom chip of the stack and the base on the one hand and / or as a protective packaging on the other.
  • Fig. 11C shows a variant of the chip stack shown in Fig. 11B.
  • the variant shown in FIG. 11C represents a particularly preferred embodiment.
  • This embodiment differs from the embodiment shown in FIG. 11B in that here the conductive channels 31 do not come from the side which has the active layer 11, but at all through-contacted chips of the chip stack were inserted from the opposite side.
  • the insulating layers 32 shown in FIGS. 3C and 3D have been omitted.
  • the multilayer integrated circuit arrangements described with reference to FIGS. 11A to 11C which are additionally at least partially covered by protection or surrounded by a housing, represent packaged multipackages.
  • the housing consists of all parts of the package
  • Multipackages that cover the chips such as the transparent cover 20, the Epoxidharzummantelung 40 or a lower adhesive layer 45th
  • FIG. 12 shows a cross-section of an embodiment in which a plurality of chips associated with a wafer in the wafer assembly share a via.
  • the chips for the top position in the stack, which have been produced in the wafer assembly on a wafer 110, are explained in accordance with the FIGS. 1A to IE
  • a metal layer 18 is applied which connects pads 25A, 25B to the etch pit 17, the pads 25A and 25B being connected to the active layers 11A, 11B of two different devices in the wafer assembly.
  • the contacts are redistributed as shown in Figure 2B or 2C.
  • the redistributed contacts are connected when connecting the wafer 110, 120 with the contact surfaces 25 of the building blocks of the respective underlying wafer.
  • the wafers can be separated after joining along parting lines 41 from the wafer assembly, which runs centrally through the common via. After disconnecting the chip stack, this results in no via, but rather a contact that runs around the edge of the substrate of a chip in the chip stack.
  • a chip stack produced according to one of the embodiments described above can be further processed after completion with a known method.
  • the chip stack, or the multilayer semiconductor device with methods of SMD technology can be directly connected to a circuit board or cast in a suitable housing for SMD or through-hole techniques.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé pour établir des connexions de contact électriques pour au moins un composant intégré à un matériau support qui présente une première zone superficielle, au moins un contact de raccordement étant disposé au moins partiellement dans cette première zone superficielle pour chaque composant. Ce procédé se caractérise en particulier en ce qu'un élément de recouvrement est placé sur la première zone superficielle et en ce qu'au moins un canal de contact s'étend dans le matériau support perpendiculairement à la première zone superficielle. Pour former au moins un point de contact dans une deuxième zone superficielle à préparer, au moins une connexion de contact électrique est établie par l'intermédiaire des canaux de contact respectifs entre le point de contact et au moins un des contacts de raccordement. De façon extrêmement avantageuse, on peut produire un point de contact de ce type sur la face du matériau support opposée au contact de raccordement et ainsi sur la face du matériau support opposée à la surface active un point de contact connecté électriquement au contact de raccordement. Cette technique remplace la technique antérieure selon laquelle les tranchées s'étendent le long du matériau support et l'établissement de contacts s'effectue latéralement autour du composant.
EP02796172A 2001-08-24 2002-08-26 Procede d'etablissement de contacts et boitiers de circuits integres Withdrawn EP1419534A2 (fr)

Priority Applications (1)

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EP10011997A EP2287916A3 (fr) 2001-08-24 2002-08-26 Connexion et logement des modules à circuits integrés

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DE2001141571 DE10141571B8 (de) 2001-08-24 2001-08-24 Verfahren zum Zusammenbau eines Halbleiterbauelements und damit hergestellte integrierte Schaltungsanordnung, die für dreidimensionale, mehrschichtige Schaltungen geeignet ist
DE10141558 2001-08-24
DE10141571 2001-08-24
DE10141558 2001-08-24
DE10225373 2002-06-06
DE10225373A DE10225373A1 (de) 2001-08-24 2002-06-06 Verfahren zum Kontaktieren und Gehäusen von integrierten Schaltungen
PCT/EP2002/009498 WO2003019653A2 (fr) 2001-08-24 2002-08-26 Procede d'etablissement de contacts et boitiers de circuits integres

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EP02796172A Withdrawn EP1419534A2 (fr) 2001-08-24 2002-08-26 Procede d'etablissement de contacts et boitiers de circuits integres

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EP (2) EP2287916A3 (fr)
JP (2) JP4499412B2 (fr)
KR (1) KR100638379B1 (fr)
CN (2) CN100578816C (fr)
AU (1) AU2002356147A1 (fr)
IL (2) IL160189A0 (fr)
WO (1) WO2003019653A2 (fr)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094082A (ja) * 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
AU2002356147A1 (en) * 2001-08-24 2003-03-10 Schott Glas Method for producing contacts and printed circuit packages
US7074638B2 (en) 2002-04-22 2006-07-11 Fuji Photo Film Co., Ltd. Solid-state imaging device and method of manufacturing said solid-state imaging device
EP1942522A3 (fr) * 2002-07-29 2009-11-11 FUJIFILM Corporation Dispositif d'imagerie à l'état solide et procédé de fabrication de ce dispositif d'imagerie à l'état solide
JP4071615B2 (ja) * 2002-12-20 2008-04-02 株式会社フジクラ 貫通電極の形成方法及び貫通電極付き基板
JP4289146B2 (ja) * 2003-03-27 2009-07-01 セイコーエプソン株式会社 三次元実装型半導体装置の製造方法
US20040199052A1 (en) 2003-04-01 2004-10-07 Scimed Life Systems, Inc. Endoscopic imaging system
DE102004015654A1 (de) * 2003-04-02 2004-10-21 Luk Lamellen Und Kupplungsbau Beteiligungs Kg Endstufe zum Ansteuern einer elektrischen Maschine
EP1482553A3 (fr) * 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Dispositif semi-conducteur et méthode de fabrication associée
JP4130158B2 (ja) 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
DE10356885B4 (de) 2003-12-03 2005-11-03 Schott Ag Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement
JP4307284B2 (ja) * 2004-02-17 2009-08-05 三洋電機株式会社 半導体装置の製造方法
JP4331033B2 (ja) * 2004-03-29 2009-09-16 浜松ホトニクス株式会社 半導体光検出素子及びその製造方法
JP3875240B2 (ja) * 2004-03-31 2007-01-31 株式会社東芝 電子部品の製造方法
KR100676493B1 (ko) * 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
TWI264807B (en) * 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI244186B (en) * 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7285434B2 (en) * 2005-03-09 2007-10-23 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
EP1713126A1 (fr) * 2005-04-14 2006-10-18 Shih-Hsien Tseng Dispositif de prise d'images et méthode pour sa fabrication
EP1734583A1 (fr) 2005-06-14 2006-12-20 Photonis-DEP B.V. Capteur à bombardement d'électrons et méthode de fabrication associée
DE102005036824A1 (de) * 2005-08-04 2007-03-29 Siemens Ag Chipmodul zum Einbau in Sensorchipkarten für fluidische Anwendungen sowie Verfahren zur Herstellung eines derartigen Chipmoduls
US20070090156A1 (en) * 2005-10-25 2007-04-26 Ramanathan Lakshmi N Method for forming solder contacts on mounted substrates
US7393758B2 (en) * 2005-11-03 2008-07-01 Maxim Integrated Products, Inc. Wafer level packaging process
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
JP5555400B2 (ja) * 2006-08-04 2014-07-23 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置及びその製造方法
US7723224B2 (en) * 2006-06-14 2010-05-25 Freescale Semiconductor, Inc. Microelectronic assembly with back side metallization and method for forming the same
EP1885019A1 (fr) * 2006-07-24 2008-02-06 Schott Advanced Packaging Singapore Te. Ltd. Méthode de fabrication d'une antenne RFID tridimensionelle et dispositif ainsi formé
US8238678B2 (en) * 2006-08-30 2012-08-07 Siemens Medical Solutions Usa, Inc. Providing representative image information
US7271485B1 (en) 2006-09-11 2007-09-18 Agere Systems Inc. Systems and methods for distributing I/O in a semiconductor device
KR100832845B1 (ko) * 2006-10-03 2008-05-28 삼성전자주식회사 반도체 패키지 구조체 및 그 제조 방법
JP5010247B2 (ja) * 2006-11-20 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4958273B2 (ja) * 2007-01-23 2012-06-20 オンセミコンダクター・トレーディング・リミテッド 発光装置及びその製造方法
US7576425B2 (en) * 2007-01-25 2009-08-18 Xintec, Inc. Conducting layer in chip package module
US8049326B2 (en) 2007-06-07 2011-11-01 The Regents Of The University Of Michigan Environment-resistant module, micropackage and methods of manufacturing same
US10266392B2 (en) 2007-06-07 2019-04-23 E-Pack, Inc. Environment-resistant module, micropackage and methods of manufacturing same
JP2009016623A (ja) * 2007-07-05 2009-01-22 Olympus Corp 半導体パッケージ
TWI353667B (en) * 2007-07-13 2011-12-01 Xintec Inc Image sensor package and fabrication method thereo
US8772919B2 (en) 2007-08-08 2014-07-08 Wen-Cheng Chien Image sensor package with trench insulator and fabrication method thereof
TWI345830B (en) * 2007-08-08 2011-07-21 Xintec Inc Image sensor package and fabrication method thereof
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
KR101348748B1 (ko) * 2007-08-24 2014-01-08 삼성전자주식회사 재배선 기판을 이용한 반도체 패키지 제조방법
US7691747B2 (en) * 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
JP2009224492A (ja) * 2008-03-14 2009-10-01 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
US7880293B2 (en) * 2008-03-25 2011-02-01 Stats Chippac, Ltd. Wafer integrated with permanent carrier and method therefor
US7648911B2 (en) * 2008-05-27 2010-01-19 Stats Chippac, Ltd. Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias
DE102008025756B4 (de) * 2008-05-29 2023-02-23 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiteranordnung
US7932180B2 (en) * 2008-07-07 2011-04-26 Infineon Technologies Ag Manufacturing a semiconductor device via etching a semiconductor chip to a first layer
DE102008039360B4 (de) * 2008-08-22 2021-05-12 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
US8097525B2 (en) * 2008-08-29 2012-01-17 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
US7923350B2 (en) * 2008-09-09 2011-04-12 Infineon Technologies Ag Method of manufacturing a semiconductor device including etching to etch stop regions
US8137995B2 (en) * 2008-12-11 2012-03-20 Stats Chippac, Ltd. Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures
JP2010245292A (ja) * 2009-04-06 2010-10-28 Panasonic Corp 光学デバイス、電子機器、及びその製造方法
US8485966B2 (en) 2009-05-08 2013-07-16 Boston Scientific Scimed, Inc. Endoscope with distal tip having encased optical components and display orientation capabilities
EP2421678B1 (fr) 2009-04-23 2018-11-28 John S. Sroka Clé à rochet
EP2246890B1 (fr) * 2009-04-28 2013-03-13 STMicroelectronics (Crolles 2) SAS Mode de réalisation d'un module de capture d'images
JP2011009645A (ja) * 2009-06-29 2011-01-13 Toshiba Corp 半導体装置及びその製造方法
CN101716744B (zh) * 2009-11-12 2012-01-18 博敏电子股份有限公司 无环盲孔高密度互连印制线路板板面整平的方法
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
TWI419302B (zh) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng 封裝製程
JP5218455B2 (ja) * 2010-03-17 2013-06-26 株式会社デンソー 半導体力学量センサおよびその製造方法
US8564141B2 (en) * 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
TWI536525B (zh) * 2010-05-11 2016-06-01 精材科技股份有限公司 晶片封裝體
US8193610B2 (en) * 2010-08-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP
CN102041531B (zh) * 2010-12-30 2012-05-23 东莞铭励电器制品有限公司 一种局部喷镀银接触钉之喷镀装置及一种局部喷镀银接触钉
JP2013118230A (ja) * 2011-12-01 2013-06-13 Canon Inc 固体撮像装置
FR2987892B1 (fr) * 2012-03-06 2014-04-18 Auxitrol Sa Procede de fabrication d'un capteur de pression et capteur correspondant
EP2657691B1 (fr) 2012-04-25 2018-08-29 E+E Elektronik Ges.m.b.H. Agencement de détecteur d'humidité
US9165792B2 (en) * 2012-09-25 2015-10-20 Infineon Technologies Ag Integrated circuit, a chip package and a method for manufacturing an integrated circuit
US9520378B2 (en) * 2012-12-21 2016-12-13 Intel Corporation Thermal matched composite die
US20150221523A1 (en) 2013-10-01 2015-08-06 Infineon Technologies Ag Arrangement and method for manufacturing the same
US9196568B2 (en) * 2013-10-01 2015-11-24 Infineon Technologies Ag Arrangement and method for manufacturing the same
FR3014242A1 (fr) * 2013-11-29 2015-06-05 St Microelectronics Grenoble 2 Dispositif electronique comprenant une puce de circuits integres et une plaque optique empilees
SG10201408698SA (en) * 2013-12-26 2015-07-30 Agency Science Tech & Res Chemical Sensor Package For Highly Pressured Environment
CN104465564B (zh) * 2014-01-06 2017-09-15 昆山西钛微电子科技有限公司 晶圆级芯片tsv封装结构及其封装方法
NO2777050T3 (fr) * 2014-02-25 2018-06-16
DE102014111945A1 (de) * 2014-05-19 2015-11-19 Zentrum Mikroelektronik Dresden Ag Funktionseinheit mit strahlungsundurchlässigen Mitteln
GB2534191A (en) * 2015-01-16 2016-07-20 Mahle Int Gmbh Sliding bearing
US20170147857A1 (en) * 2015-11-23 2017-05-25 Xintec Inc. Chip package and method for forming the same
CN107946335B (zh) 2017-12-22 2020-10-27 成都先锋材料有限公司 一种cmos影像传感封装结构及其制作方法
CN108155198B (zh) * 2017-12-22 2021-04-02 成都先锋材料有限公司 一种cmos影像传感封装结构及其制作方法
JP7246136B2 (ja) * 2018-02-14 2023-03-27 キヤノン株式会社 半導体装置、カメラおよび半導体装置の製造方法
JP7158179B2 (ja) * 2018-05-30 2022-10-21 シャープ株式会社 半導体チップ積層体および半導体チップ積層体の製造方法
CN111508926B (zh) 2019-01-31 2022-08-30 奥特斯(中国)有限公司 一种部件承载件以及制造部件承载件的方法
DE102019211002B4 (de) 2019-07-19 2024-01-18 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Optisches system und verfahren zum herstellen eines optischen systems
DE102019210747B4 (de) 2019-07-19 2023-11-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Optisches system und verfahren zum herstellen eines optischen systems
KR20220021238A (ko) 2020-08-13 2022-02-22 삼성전자주식회사 반도체 패키지 및 그 제조방법

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648131A (en) * 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
JPS63193545A (ja) * 1987-02-06 1988-08-10 Toshiba Corp 半導体集積回路の製造方法
US5463246A (en) * 1988-12-29 1995-10-31 Sharp Kabushiki Kaisha Large scale high density semiconductor apparatus
JPH0321859A (ja) 1989-06-20 1991-01-30 Nippondenso Co Ltd 酸素センサー
JPH085566Y2 (ja) * 1989-07-12 1996-02-14 オリンパス光学工業株式会社 固体撮像装置
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
JP3077034B2 (ja) * 1990-07-25 2000-08-14 セイコーインスツルメンツ株式会社 半導体イメージセンサ装置
JPH04279035A (ja) * 1991-03-07 1992-10-05 Nikko Kyodo Co Ltd 電界効果トランジスタの製造方法
JPH05304190A (ja) * 1992-04-28 1993-11-16 Rohm Co Ltd 半導体装置
US5244817A (en) * 1992-08-03 1993-09-14 Eastman Kodak Company Method of making backside illuminated image sensors
US5330918A (en) * 1992-08-31 1994-07-19 The United States Of America As Represented By The Secretary Of The Navy Method of forming a high voltage silicon-on-sapphire photocell array
JPH06113214A (ja) * 1992-09-28 1994-04-22 Olympus Optical Co Ltd 固体撮像装置
GB2279808B (en) * 1993-01-19 1996-11-20 Hughes Aircraft Co Thermally matched readout/detector assembly and method for fabricating same
JPH06244437A (ja) * 1993-02-17 1994-09-02 Oki Electric Ind Co Ltd 半導体ウエハ
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5695933A (en) * 1993-05-28 1997-12-09 Massachusetts Institute Of Technology Direct detection of expanded nucleotide repeats in the human genome
JP2713113B2 (ja) * 1993-08-17 1998-02-16 日本電気株式会社 半導体装置の製造方法
DE69507284T2 (de) 1994-11-22 1999-07-01 Philips Electronics N.V., Eindhoven Halbleiter mit einem träger auf dem ein substrat mit einem halbleiter-element mittels einer klebeschicht und ein leiterbahn-muster befestigt sind
JP3186941B2 (ja) * 1995-02-07 2001-07-11 シャープ株式会社 半導体チップおよびマルチチップ半導体モジュール
US5610431A (en) * 1995-05-12 1997-03-11 The Charles Stark Draper Laboratory, Inc. Covers for micromechanical sensors and other semiconductor devices
US5682062A (en) * 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
JP3376203B2 (ja) 1996-02-28 2003-02-10 株式会社東芝 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法
US5682065A (en) * 1996-03-12 1997-10-28 Micron Technology, Inc. Hermetic chip and method of manufacture
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
DE19621614C1 (de) 1996-05-30 1997-12-18 Itt Cannon Gmbh Steckverbinder
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
US5766979A (en) * 1996-11-08 1998-06-16 W. L. Gore & Associates, Inc. Wafer level contact sheet and method of assembly
US6051489A (en) 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
JP3648585B2 (ja) * 1997-05-27 2005-05-18 カシオ計算機株式会社 半導体装置及びその製造方法
DE19746641B4 (de) 1997-09-19 2006-02-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verdrahtungsverfahren für Halbleiter-Bauelemente zur Verhinderung von Produktpiraterie und Produktmanipulation und Verwendung des Halbleiter-Bauelements in einer Chipkarte
US6037822A (en) * 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
JPH11150113A (ja) * 1997-11-17 1999-06-02 Nec Corp 半導体装置の製造方法
IL123207A0 (en) * 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
JP4063944B2 (ja) * 1998-03-13 2008-03-19 独立行政法人科学技術振興機構 ３次元半導体集積回路装置の製造方法
GB9813778D0 (en) * 1998-06-25 1998-08-26 Univ Cambridge Tech Assay methods and means
US6393183B1 (en) * 1998-08-13 2002-05-21 Eugene Robert Worley Opto-coupler device for packaging optically coupled integrated circuits
US6515355B1 (en) * 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
DE19846232A1 (de) 1998-09-03 2000-03-09 Fraunhofer Ges Forschung Verfahren zur Herstellung eines Halbleiterbauelements mit Rückseitenkontaktierung
JP2000195861A (ja) * 1998-12-25 2000-07-14 Texas Instr Japan Ltd 半導体装置およびその製造方法
US6338284B1 (en) * 1999-02-12 2002-01-15 Integrated Sensing Systems (Issys) Inc. Electrical feedthrough structures for micromachined devices and methods of fabricating the same
DE19916572A1 (de) * 1999-04-13 2000-10-26 Siemens Ag Optisches Halbleiterbauelement mit optisch transparenter Schutzschicht
DE19918671B4 (de) 1999-04-23 2006-03-02 Giesecke & Devrient Gmbh Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung
DE19958486A1 (de) 1999-05-27 2000-12-07 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration von elektrischen Bauelementen mittels Rückseitenkontakt
US6541987B1 (en) * 1999-08-30 2003-04-01 Advanced Micro Devices, Inc. Laser-excited detection of defective semiconductor device
JP2001177081A (ja) * 1999-12-15 2001-06-29 Toshiba Corp 半導体装置
JP3858545B2 (ja) * 1999-12-27 2006-12-13 セイコーエプソン株式会社 半導体モジュール及び電子機器
US6384353B1 (en) * 2000-02-01 2002-05-07 Motorola, Inc. Micro-electromechanical system device
US6780661B1 (en) * 2000-04-12 2004-08-24 Finisar Corporation Integration of top-emitting and top-illuminated optoelectronic devices with micro-optic and electronic integrated circuits
JP3713418B2 (ja) * 2000-05-30 2005-11-09 光正 小柳 ３次元画像処理装置の製造方法
JP2001351997A (ja) * 2000-06-09 2001-12-21 Canon Inc 受光センサーの実装構造体およびその使用方法
JP2002026012A (ja) * 2000-07-05 2002-01-25 Murata Mfg Co Ltd 半導体装置及びその製造方法
JP2002094082A (ja) * 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
US20020135069A1 (en) * 2000-11-03 2002-09-26 Wood Robert L. Electroplating methods for fabricating microelectronic interconnects
US6580858B2 (en) * 2001-04-30 2003-06-17 Xerox Corporation Micro-opto-electro-mechanical system (MOEMS)
US6660614B2 (en) * 2001-05-04 2003-12-09 New Mexico Tech Research Foundation Method for anodically bonding glass and semiconducting material together
US6461888B1 (en) * 2001-06-14 2002-10-08 Institute Of Microelectronics Lateral polysilicon beam process
US6943451B2 (en) * 2001-07-02 2005-09-13 International Business Machines Corporation Semiconductor devices containing a discontinuous cap layer and methods for forming same
US6503793B1 (en) * 2001-08-10 2003-01-07 Agere Systems Inc. Method for concurrently forming an ESD protection device and a shallow trench isolation region
AU2002356147A1 (en) * 2001-08-24 2003-03-10 Schott Glas Method for producing contacts and printed circuit packages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03019653A2 *

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US20100065883A1 (en) 2010-03-18
JP5329996B2 (ja) 2013-10-30
EP2287916A3 (fr) 2012-01-25
CN101714516A (zh) 2010-05-26
JP2005501414A (ja) 2005-01-13
WO2003019653A3 (fr) 2003-11-20
AU2002356147A1 (en) 2003-03-10
US20110021002A1 (en) 2011-01-27
US8349707B2 (en) 2013-01-08
IL160189A0 (en) 2004-07-25
CN100578816C (zh) 2010-01-06
CN1547778A (zh) 2004-11-17
US20130137259A1 (en) 2013-05-30
US7821106B2 (en) 2010-10-26
US20050042786A1 (en) 2005-02-24
WO2003019653A2 (fr) 2003-03-06
US20030113979A1 (en) 2003-06-19
US20080150063A1 (en) 2008-06-26
JP2009094540A (ja) 2009-04-30
US7700957B2 (en) 2010-04-20
US7880179B2 (en) 2011-02-01
EP2287916A2 (fr) 2011-02-23
JP4499412B2 (ja) 2010-07-07
KR20040036735A (ko) 2004-04-30
US6911392B2 (en) 2005-06-28
IL160189A (en) 2007-12-03
KR100638379B1 (ko) 2006-10-26
AU2002356147A8 (en) 2003-03-10

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